AD7304BN AD [Analog Devices], AD7304BN Datasheet - Page 4

• Manufacturer Part Number: AD7304BN
• Description: +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
• Manufacturer: AD [Analog Devices]

AD7304/AD7305
CS
H
L
↑+
H
H
H
NOTES
1
2
3
AD7304 SAC
If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.
↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).
LDAC is a level-sensitive input.
CLK
X
↑+
L
X
X
X
MSB
B11
LDAC CLR
H
H
H
L
H
H
Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
B10
SDC
V
H
H
H
H
↓–
↑+
OUT
LDAC
LDAC
CLR
CLK
CLK
SDI
SDI
CS
FS
ZS
B9
A1
Serial Shift Register Function
No Effect
Data Advanced 1 Bit
No Effect
No Effect
No Effect
No Effect
t
LD1
SDI/SHDN
SA
A0
B8
t
I
CSS
DD
SI
Table I. AD7304 Control Logic Truth Table
Figure 2. AD7304 Timing Diagram
Figure 3. AD7304 Timing Diagram
A1
t
CL
B7
D7
t
DS
A0
t
SDN
t
DH
D7
t
CH
B6
D6
D6
–4–
Input REG Function
No Effect
No Effect
Updated with SR Contents
Latched with SR Contents
Loaded with 00
Latched with 00
D5
B5
D5
t
LDW
D4
t
S
B4
D4
D3
H
H
t
SDR
D2
ERROR BAND
B3
D3
2
t
D1
1 LSB
2
CSH
DAC Register Function
No Effect
No Effect
No Effect
All Input Register Contents Transferred
Loaded with 00
Latched with 00
D0
t
t
LD2
CLRW
t
B2
D2
S
B1
D1
H
H
LSB
B0
D0
REV. A
3