AD7304BN AD [Analog Devices], AD7304BN Datasheet - Page 6

• Manufacturer Part Number: AD7304BN
• Description: +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
• Manufacturer: AD [Analog Devices]

AD7304/AD7305
Pin # Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin # Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
V
V
V
V
GND
LDAC
CLR
CS
CLK
SDI/SHDN
V
V
V
V
V
V
V
V
V
GND
LDAC
DB7
DB6
DB5
DB4
DB3
DB2
DB1
WR
A1
A0/SHDN
V
V
V
DB0
OUT
OUT
SS
REF
REF
REF
REF
DD
OUT
OUT
OUT
OUT
SS
REF
DD
OUT
OUT
A
B
D
C
B
A
D
C
B
A
D
C
Function
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
Channel A Reference Input. Establishes V
Channel B Reference Input. Establishes V
Common Analog and Digital Ground.
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the
decoded Input Register when CS returns HIGH. Does not effect LDAC operation.
Clock input, positive edge clocks data into shift register. Disabled by chip select CS.
Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active
when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is
present on V
Channel D Reference Input. Establishes V
Channel C Reference Input. Establishes V
Positive power supply input. Specified range of operation +2.7 V to +5.5 V.
Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Function
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
Channel B Reference Input. Establishes V
Common Analog and Digital Ground.
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
MSB Digital Input Data Bit.
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
LSB Digital Input Data Bit.
Write data into Input Register control line, active low. See Control Logic Truth Table for operation.
Address Bit 1.
Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.
Does not effect DAC register contents as long as power is present on V
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V
is open circuit when SHDN is enabled.
DD
.
AD7304 PIN FUNCTION DESCRIPTIONS
AD7305 PIN FUNCTION DESCRIPTIONS
OUT
OUT
OUT
OUT
OUT
A full-scale voltage. Specified range of operation V
B full-scale voltage. Specified range of operation V
C full-scale voltage. Specified range of operation V
D full-scale voltage. Specified range of operation V
–6–
full-scale voltage. Specified range of operation V
DD
.
SS
SS
SS
SS
< V
< V
< V
SS
< V
< V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
A < V
B < V
C < V
D < V
B pin. Output
B pin. Output
A pin. Output
A pin. Output
D pin. Output
C pin. Output
C pin. Output
D pin. Output
< V
DD
DD
DD
DD
DD
.
REV. A
.
.
.
.