CY7C1215F-133AC CYPRESS [Cypress Semiconductor], CY7C1215F-133AC Datasheet - Page 12

• Manufacturer Part Number: CY7C1215F-133AC
• Description: 1-Mb (32K x 32) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05421 Rev. **
Switching Waveforms
Write Cycle Timing
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data In (D)
ADDRESS
BW[A :D]
ADSP
ADSC
BWE,
ADV
CLK
GW
OE
CE
BURST READ
High-Z
[17, 18]
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
(continued)
t ADS
t CL
t DS
Single WRITE
D(A1)
t ADH
t DH
A2
D(A2)
DON’T CARE
t WES
D(A2 + 1)
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
[A : D]
ADV suspends burst
LOW .
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t
ADVS
t WES
Extended BURST WRITE
CY7C1215F
D(A3 + 1)
t
t WEH
ADVH
Page 12 of 16
D(A3 + 2)