MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 32

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 23:
PRECHARGE
Figure 24:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Terminating a WRITE Burst
PRECHARGE Command
Note:
COMMAND
The PRECHARGE command shown in Figure 24 is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
A0–A9, A11, A12
ADDRESS
DQMs are LOW.
BA0, BA1
CLK
DQ
Transitioning Data
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
BANK,
COL n
WRITE
D
T0
HIGH
n
IN
TERMINATE
BURST
T1
Bank Selected
All Banks
ADDRESS
32
BANK
COMMAND
(ADDRESS)
Don’t Care
(DATA)
T2
NEXT
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP) after the PRECHARGE command is issued.
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Operations