CY7C138 CYPRESS [Cypress Semiconductor], CY7C138 Datasheet - Page 7

• Manufacturer Part Number: CY7C138
• Description: 4K x 8/9 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes:
19. BUSY = HIGH for the writing port.
20. CE
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
23. R/W must be HIGH during all address transitions.
SEM OR CE
Read Timing with Port-to-Port Delay (M/S = L)
ADDRESS
ADDRESS
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
DATA OUT
ADDRESS
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
bus for the required t
t
DATA
PWE
DATA
DATA IN
L
= CE
.
R/W
R/W
OUTL
OE
INR
R
R
R
= LOW.
L
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified
(continued)
t
SA
t
HZOE
[19, 20]
t
MATCH
SCE
MATCH
t
t
HIGH IMPEDANCE
AW
WC
7
t
WC
t
PWE
[21, 22, 23]
t
PWE
PWE
or (t
HZWE
t
WDD
t
t
VALID
SD
SD
DATA VALID
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on the
t
DDD
t
HD
t
HD
t
LZOE
t
HA
CY7C138
CY7C139
VALID
C138-10
C138-11