CY7C1355C-100AXI CYPRESS [Cypress Semiconductor], CY7C1355C-100AXI Datasheet
CY7C1355C-100AXI
Related parts for CY7C1355C-100AXI
CY7C1355C-100AXI Summary of contents
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... For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05539 Rev. *E 9-Mbit (256K x 36/512K x 18) Functional Description The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the ...
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... Logic Block Diagram – CY7C1355C (256K x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1357C (512K x 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ...
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... BYTE DDQ DQP 30 D Document #: 38-05539 Rev. *E 100-Pin TQFP Pinout CY7C1355C CY7C1355C CY7C1357C 80 DQP DDQ BYTE ...
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... V 20 DDQ DQP DDQ Document #: 38-05539 Rev. *E 100-Pin TQFP Pinout CY7C1357C CY7C1355C CY7C1357C DDQ DQP DDQ 69 DQ ...
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... DDQ DDQ DDQ NC/144M T NC/72M U V DDQ Document #: 38-05539 Rev. *E CY7C1355C (256K x 36 NC/18M ADV/ DQP ...
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... B DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document #: 38-05539 Rev. *E CY7C1355C (256K x 36 CEN CLK ...
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... CE to select/deselect the device and CE to select/deselect the device and DQP s is controlled by BW correspondingly left floating selects interleaved burst sequence. DD CY7C1355C CY7C1357C are placed in a tri-state condition.The X . During s through a pull up resistor. DD Page [+] Feedback [+] Feedback ...
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... Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355C/CY7C1357C is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP Doing so will tri-state the output drivers ...
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... X the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1355C/CY7C1357C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... Truth Table Operation NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SLEEP MODE Partial Truth Table for Read/Write Function (CY7C1355C) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance ...
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... TDI and TDO in the shift-DR controller state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1355C CY7C1357C Page [+] Feedback [+] Feedback ...
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... Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 38-05539 Rev CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description / ns CY7C1355C CY7C1357C TDOV Min. Max. Unit MHz ...
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... Reserved for Internal Use 001001 001001 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor 1 1 Indicates the presence register CY7C1355C CY7C1357C to 2.5V SS 1.25V 50Ω 50Ω 20pF O < +70° 3.3V ± 0.165V unless A DD Min ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05539 Rev. *E Bit Size (x36) Bit Size (x18 Description CY7C1355C CY7C1357C Page [+] Feedback [+] Feedback ...
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... BGA Boundary Scan Order CY7C1355C (256K x 36) Signal Bit# ball ID Name Bit# ball ID 1 CLK CEN ADV/ DQP ...
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... FBGA Boundary Scan Order CY7C1355C (256K x 36) Signal Bit# ball ID Name Bit# ball CLK CEN ADV/ B10 A10 C11 DQP E10 F10 G10 ...
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... inputs /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1355C CY7C1357C + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – Min. Max. Unit 3.135 3 ...
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... R = 317Ω 3.3V V DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1355C CY7C1357C 119 BGA 165 FBGA Max. Max. Unit 119 BGA 165 FBGA Package ...
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... DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355C CY7C1357C –133 –100 Max. Min. Max. Unit 4.0 ns 4.0 ns 6.5 7 ...
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... CDV t DOH t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355C CY7C1357C OEV t CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH. 2 ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05539 Rev CDV t DOH t OEV t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED CY7C1355C CY7C1357C CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) Page [+] Feedback [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05539 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1355C CY7C1357C Page [+] Feedback [+] Feedback ...
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... CY7C1355C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1357C-100BZC CY7C1355C-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1357C-100BZXC CY7C1355C-100AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1357C-100AXI CY7C1355C-100BGI 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1357C-100BGI CY7C1355C-100BGXI 51-85115 119-ball Ball Grid Array ( ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1355C CY7C1357C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0 ...
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... 0.70 REF. 12.00 30° TYP. SEATING PLANE C Document #: 38-05539 Rev. *E 119-Ball BGA ( 2.4 mm) (51-85115) Ø1.00(3X) REF 0.15(4X) CY7C1355C CY7C1357C Ø0. Ø0. Ø0.75±0.15(119X ...
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... SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1355C CY7C1357C BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø ...
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... Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05539 Orig. of REV. ECN NO. Issue Date Change ** 242032 See ECN *A 332059 See ECN *B 351895 See ECN *C 377095 See ECN *D 408298 See ECN *E 501793 See ECN Document #: 38-05539 Rev ...