CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet
CY7C1355C-100AC
Related parts for CY7C1355C-100AC
CY7C1355C-100AC Summary of contents
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... Document #: 38-05539 Rev. ** PRELIMINARY 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the CY7C1355C/CY7C1357C is equipped with the advanced No ...
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... Logic Block Diagram – CY7C1355C (256K x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ ADDRESS BW A0, A1 REGISTER BW C MODE CLK C CEN OE CE1 CE2 CE3 ZZ ADV/ Logic Block Diagram – CY7C1357C (512K x 18) WE ADDRESS A0, A1, A REGISTER ...
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... BYTE DDQ DQP 30 D Document #: 38-05539 Rev. ** PRELIMINARY 100-lead TQFP CY7C1355C CY7C1355C CY7C1357C 80 DQP DDQ BYTE ...
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... V 20 DDQ DQP DDQ Document #: 38-05539 Rev. ** PRELIMINARY 100-lead TQFP CY7C1357C CY7C1355C CY7C1357C DDQ DQP DDQ 69 DQ ...
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... DDQ DDQ 72M U V DDQ Document #: 38-05539 Rev. ** PRELIMINARY 119-ball BGA (3 Chip Enables with JTAG) CY7C1355C (256K x 36 18M CE A ADV/ DQP ...
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... DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05539 Rev. ** PRELIMINARY 165-ball fBGA (3 Chip enable with JTAG) CY7C1355C (256K x 36 CLK ...
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... Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to V selects interleaved burst sequence. Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. CY7C1355C CY7C1357C and DQP controlled by BW correspondingly ...
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... This pin is not available on TQFP packages Connects. Not internally connected to the die. 18M,36M, 72M, 144M and 288M are address expansion pins and are not internally connected to the die. This pin can be connected to Ground or should be left floating. CY7C1355C CY7C1357C through DD . This DD ...
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... Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355C/CY7C1357C is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP ...
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... A1 Test Conditions ZZ > V – 0. > V – 0. < 0.2V This parameter is sampled This parameter is sampled CY7C1355C CY7C1357C Second Third Fourth Address Address Address A1: A0 A1 Min. Max. ...
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... data when OE is active valid. Appropriate write will be done based on which byte write is active. X CY7C1355C CY7C1357C CEN CLK L->H Three-State L->H Three-State L->H Three-State L->H Three-State ...
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... Partial Truth Table for Read/Write Function (CY7C1355C) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes [2, 3,9] Truth Table for Read/Write ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1355C/CY7C1357Ccontains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. ...
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... SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Cap- ture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. CY7C1355C CY7C1357C Page ...
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... Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1355C CY7C1357C Page ...
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... TH t CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [10, 11] Over the operating Range Description / ns 3.3V TAP AC Output Load Equivalent to 3.3V SS TDO CY7C1355C CY7C1357C TDOV t TDOX UNDEFINED Min. Max 1.5V 50 ...
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... V = 3.3V OH DDQ V = 2.5V DDQ 3.3V OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1355C CY7C1357C 1.25V 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 –0.5 0.7 V –0.3 0.7 V –5 5 µA ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1355C CY7C1357C Description Describes the version number Reserved for Internal Use ...
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... BGA Boundary Scan Order CY7C1355C (256K x 36) BIT BALL BIT # ...
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... CY7C1357C (512K x 18) BIT CY7C1355C CY7C1357C BALL Internal Page ...
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... Boundary Scan Order CY7C1355C (256K x 36) BIT# BALL ID BIT# BALL 10N 39 C10 4 P11 P10 R10 R11 H11 N11 M11 50 B3 ...
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... Note: 16. Bit Pre-Set HIGH CY7C1355C CY7C1357C BALL Internal Page ...
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... 0.3V 0, inputs static /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1355C CY7C1357C Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% -40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... V = 3.3V 2.5V DDQ R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1355C CY7C1357C TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ...
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... DDQ is the time that the power needs to be supplied above V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355C CY7C1357C 117 MHz 100 MHz Min. Max. Min. Max 8 ...
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... CYC CDV t DOH t CLZ D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355C CY7C1357C OEV t CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ BURST WRITE READ WRITE READ D(A5) Q(A6) D(A7) Q(A4+1) is LOW HIGH ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05539 Rev. ** PRELIMINARY [26, 27, 29 CDV t DOH t CLZ D(A2) Q(A3) Q(A4) D(A2+1) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED CY7C1355C CY7C1357C OEV t CHZ Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE D(A5) Q(A6) D(A7) 10 D(A7) DESELECT Page ...
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... CY7C1357C-133AC CY7C1355C-133AI CY7C1357C-133AI CY7C1355C-133BGC CY7C1357C-133BGC CY7C1355C-133BGI CY7C1357C-133BGI CY7C1355C-133BZC CY7C1357C-133BZC CY7C1355C-133BZI CY7C1357C-133BZI 117 CY7C1355C-117AC CY7C1357C-117AC CY7C1355C-117AI CY7C1357C-117AI CY7C1355C-117BGC CY7C1357C-117BGC CY7C1355C-117BGI CY7C1357C-117BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05539 Rev. ** PRELIMINARY ZZI I ...
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... Ordering Information (continued) Speed (MHz) Ordering Code CY7C1355C-117BZC CY7C1357C-117BZC CY7C1355C-117BZI CY7C1357C-117BZI 100 CY7C1355C-100AC CY7C1357C-100AC CY7C1355C-100AI CY7C1357C-100AI CY7C1355C-100BGC CY7C1357C-100BGC CY7C1355C-100BGI ICY7C1357C-100BGI CY7C1355C-100BZC CY7C1357C-100BZC CY7C1355C-100BZI CY7C1357C-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05539 Rev. ** ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05539 Rev. ** PRELIMINARY CY7C1355C CY7C1357C 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05539 Rev. ** PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1355C CY7C1357C 51-85115-*B Page ...
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Package Diagrams (continued) NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: ...