ICS9158-05M ICST [Integrated Circuit Systems], ICS9158-05M Datasheet - Page 2
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ICS9158-05M
Manufacturer Part Number
ICS9158-05M
Description
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
1.ICS9158-05M.pdf
(7 pages)
ICS9158-05
Pin Configuration
* Input pin has internal pull-up to VDD.
Advanced Information
Pin Descriptions for ICS9158-05
PIN NUMBER
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
REFCLK
X2
X1
VDD
GND
KEYBD
FLOPPY
BUS0
AGND
OE
BUS1
GND
CPU0
CPU1
PD#
AVDD
BUS2
BUS3
GND
VDD
CPU2
BUS4
FS1
FS0
24-Pin SOIC
PIN NAME
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
14.318 clock output.
Crystal connection, which includes output crystal load capacitance.
Crystal connection, which includes crystal load capacitance and feedback bias
for a nominal 14.31818 MHz parallel-resonance 12pF crystal.
Digital POWER SUPPLY.
Digital GROUND.
12 MHz keyboard clock output.
24 MHz floppy disk clock output.
BUS clock output.
ANALOG GROUND.
OUTPUT ENABLE. Tristates all outputs when low.*
BUS clock output.
Digital GROUND.
CPU clock output.
CPU clock output.
Power-down input shuts off both PLL stages when low.*
ANALOG power supply.
CPU clock output.
BUS clock output.
Digital GROUND.
Digital POWER SUPPLY.
CPU clock output.
BUS clock output.
Clock frequency select #1.*
Clock frequency select #0.*
Functionality
PD# forces all outputs low and powers-down the oscillator and PLL
circuitry, minimizing power consumption. In order to ensure glitch-free start
and stop of the CPU and BUS clocks, PD# should be asserted after the
CPU and BUS clocks have stopped, and be deasserted 10ms (maximum
PLL lock time) prior to starting the clocks.
VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated
2
OE
OE
1
1
0
1
1
1
1
1
0
PD#
PD#
X
1
1
1
1
0
X
1
0
FS1
FLOPPY (MHz)
X
X
0
0
1
1
DESCRIPTION
Tristate
FS0
Low
X
X
24
0
1
0
1
42/10xX1
14/4xX1
14/3xX1
DOWN)
(STOP)
(PWR
Ratio
CPU
-
KEYBD (MHz)
Tristate
X1,X2,
Tristate Tristate Tristate
(MHz)
14.318
14.318
14.318
14.318
Low
REF
Low
12
(MHz)
*Low
CPU
(0:2)
Low
66.7
50
60
(MHz)
*Low
BUS
(0:4)
Low
33.3
25
30