ICS9158-05M ICST [Integrated Circuit Systems], ICS9158-05M Datasheet - Page 6

• Manufacturer Part Number: ICS9158-05M
• Manufacturer: ICST [Integrated Circuit Systems]

ICS9158-05
ICS9158-05 CPU Clock Decoding Table
(using 14.318 MHz input. All frequencies in MHz)
VDD=5V±10% or 3.3V±10%, TEMP=0-70°C
PD# forces all outputs low and powers-down the oscillator
and PLL circuitry, minimizing power consumption. In order
to ensure glitch-free start and stop of the CPU and BUS
clocks, PD# should be asserted after the CPU and BUS clocks
have stopped, and be deasserted 10ms (maximum PLL lock
time) prior to starting the clocks.
Advanced Information
OE
1
1
1
1
1
0
OE
1
1
0
PD# FS1
X
1
1
1
1
0
PD#
X
1
0
X
X
0
0
1
1
FLOPPY (MHz)
FS0
X
X
0
1
0
1
Tristate
Low
24
42/10xX1
14/4xX1
14/3xX1
DOWN)
(STOP)
(PWR
Ratio
CPU
-
KEYBD (MHz)
Tristate Tristate Tristate
X1,X2,
14.318
14.318
14.318
14.318
(MHz)
REF
Low
Tristate
Low
12
(MHz)
*Low
CPU
(0:2)
Low
66.7
50
60
(MHz)
*Low
BUS
(0:4)
Low
33.3
25
30
6
Frequency Transitions
A key feature of the ICS9158-05 is its ability to provide
smooth, glitch-free frequency transitions on the CPU and
BUS clocks when the frequency select pins are changed. The
frequency transition rate does not violate the Intel 486 or
Pentium specification of less than 0.1% frequency change
per clock period.
Using an Input Clock as a Reference
The ICS9158-05 is designed to accept a 14.318 MHz crystal
as the input reference. With some external changes, it is
possi-ble to use a crystal oscillator or other clock sources.
Please see application note AAN04 for details on driving the
ICS9158-05 with a clock.