M29W640FB STMICROELECTRONICS [STMicroelectronics], M29W640FB Datasheet - Page 15

• Manufacturer Part Number: M29W640FB
• Description: 64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block) 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W640FT, M29W640FB
3
3.1
3.2
3.3
3.4
Bus operations
Bus Read
Bus Write
Output Disable
Standby
There are five standard bus operations that control the device. These are Bus Read, Bus Write,
Output Disable, Standby and Automatic Standby. See
and
Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
High, V
Waveforms, and
valid.
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs. The
Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or
Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command
Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output
Enable must remain High, V
Waveforms, Write Enable
and
Characteristics, Chip Enable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
When Chip Enable is High, V
pins are placed in the high-impedance state. To reduce the Supply Current to the Standby
Supply Current, I
level see
During program or erase operations the memory will continue to use the Program/Erase Supply
Current, I
Table 4: Bus Operations, BYTE =
Table 14: Write AC Characteristics, Write Enable Controlled
IH
. The Data Inputs/Outputs will output the value, see
Table 12: DC
CC3
, for Program or Erase operations until the operation completes.
Table 13: Read AC
CC2
, Chip Enable should be held within V
Characteristics.
Controlled,
IH
IH
Controlled, for details of the timing requirements.
, during the whole Bus Write operation. See
, the memory enters Standby mode and the Data Inputs/Outputs
IL
, to Chip Enable and Output Enable and keeping Write Enable
Characteristics, for details of when the output becomes
Figure 11: Write AC Waveforms, Chip Enable
VIH, for a summary. Typically glitches of less than 5ns on
Table 3: Bus Operations, BYTE = VIL
CC
Figure 8: Read Mode AC
± 0.2V. For the Standby current
and
Table 15: Write AC
Figure 10: Write AC
3 Bus operations
Controlled,
IH
15/72
.