CY7C1470V25-167AXI CYPRESS [Cypress Semiconductor], CY7C1470V25-167AXI Datasheet - Page 2

• Manufacturer Part Number: CY7C1470V25-167AXI
• Description: 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *I
Selection Guide
Logic Block Diagram-CY7C1472V25 (4M x 18)
Logic Block Diagram-CY7C1474V25 (1M x 72)
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CEN
CLK
CEN
CLK
A0, A1, A
ADV/LD
MODE
BW
BW
ZZ
C
WE
CE1
CE2
CE3
OE
a
b
A0, A1, A
ADV/LD
MODE
BW
BW
BW
BW
BW
BW
BW
BW
ZZ
C
WE
CE1
CE2
CE3
OE
a
b
e
c
d
f
g
h
WRITE ADDRESS
REGISTER 1
REGISTER 0
WRITE ADDRESS
ADDRESS
REGISTER 1
Control
READ LOGIC
REGISTER 0
Sleep
ADDRESS
AND DATA COHERENCY
Control
READ LOGIC
WRITE REGISTRY
CONTROL LOGIC
Sleep
AND DATA COHERENCY
WRITE ADDRESS
ADV/LD
WRITE REGISTRY
CONTROL LOGIC
REGISTER 2
C
WRITE ADDRESS
ADV/LD
REGISTER 2
A1
A0
D1
D0
C
250 MHz
A1
A0
BURST
LOGIC
450
120
3.0
D1
D0
BURST
LOGIC
Q1
Q0
A1'
A0'
Q1
Q0
A0'
A1'
DRIVERS
WRITE
DRIVERS
WRITE
MEMORY
REGISTER 1
ARRAY
INPUT
MEMORY
REGISTER 1
ARRAY
INPUT
200 MHz
E
450
120
3.0
N
A
M
E
S
E
S
E
P
S
M
S
E
N
S
E
A
P
S
O
U
U
G
T
P
T
R
E
S
T
E
R
S
E
I
O
U
T
P
U
T
R
E
G
S
T
E
R
S
E
I
REGISTER 0
INPUT
REGISTER 0
D
A
A
N
G
T
S
T
E
E
R
I
INPUT
D
A
T
A
S
T
E
E
R
N
G
I
E
E
O
U
U
U
T
P
T
B
F
F
E
R
S
E
O
U
T
P
U
T
B
U
F
F
E
R
S
E
167 MHz
CY7C1470V25
CY7C1472V25
CY7C1474V25
400
120
3.4
DQs
DQP
DQP
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
a
b
a
b
c
d
e
f
g
h
Page 2 of 28
Unit
mA
mA
ns
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