CY7C1470V25-250AXC CYPRESS [Cypress Semiconductor], CY7C1470V25-250AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1470V25-250AXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05290 Rev. *E
Scan Register Sizes
Identification Codes
Boundary Scan Exit Order (x36)
Instruction
Bypass
ID
Boundary Scan Order–165FBGA
Boundary Scan Order–209BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Bit #
10
12
13
14
15
16
17
18
19
20
21
11
1
2
3
4
5
6
7
8
9
Register Name
165-Ball ID
Code
000
001
010
100
101
011
110
111
C1
D1
D2
G1
G2
M1
N1
M2
R1
R2
R3
E1
E2
F1
F2
K1
K2
J1
L1
J2
L2
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
tions.
PRELIMINARY
Bit Size (x36)
32
71
Boundary Scan Exit Order (x36)
3
1
–
Bit #
Description
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Bit Size (x18)
165-Ball ID
32
52
3
1
–
R10
M11
M10
P11
P10
R11
N11
K11
L11
L10
R4
R6
N6
R8
R9
P2
P6
P3
P4
P8
P9
CY7C1470V25
CY7C1472V25
CY7C1474V25
Bit Size (x72)
(continued)
Page 14 of 27
110
32
–
3
1