SI5338 SILABS [Silicon Laboratories], SI5338 Datasheet - Page 169

• Manufacturer Part Number: SI5338
• Description: I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
• Manufacturer: SILABS [Silicon Laboratories]

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Revision 0.1 to 0.2
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Revision 0.2 to 0.3
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Revision 0.3 to 0.5
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OCUMENT
Updated block diagram to show Rn output divider
and PLL bypass mode
Updated pin description to include FDBK±
Updated Table 3. DC Characteristics
Updated Table 12. Jitter Specifications
Added Supply Current vs. Output Frequency
Updated package outline specification
Clarified input clock configuration register settings
Updated DRV_INVERTn[1:0] settings
Added PLL bypass mode
Added LOS_FDBK description
Added additional detail to phase increment/
decrement and frequency increment/decrement
descriptions
Clarified output driver powerdown options
Clarified entry to self-calibration mode
Updated ordering guide
Changed minimum output clock frequency from
5 MHz to 1 MHz.
Updated slew rates.
Updated " Features" on page 1.
Updated Table 6, “Input and Output Clock
Characteristics,” on page 7.
Deleted Table 12, “Output Driver Slew Rate Control”.
Major editorial changes to all sections to improve
clarity
Completed electrical specification tables with final
characterization results
Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
Improved jitter specifications to reflect updated
characterization results
Added new Si5338N/P/Q ordering codes
Added typical application diagrams
Added an application section to highlight the
flexibility of the Si5338 in various timing functions
Added a configuration section to clarify configuration
options
C
HANGE
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Rev. 0.6
Revision 0.5 to 0.55
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Revision 0.55 to 0.6
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Editorial changes to section 3.5 “Configuring the
Si5338” to improve clarity on ordering custom
Si5338 and on configuring "blank" Si5338.
Added pin numbers to device package drawings.
Updated ordering information to include evaluation
boards.
Updated first page description and applications
Added 
Added GbE RM jitter specification with 1.875–
20 MHz integration band.
Changed output duty cycle to 45–55%.
All I
Changed ordering information to reflect 710 MHz
limit.
Info on POR and soft reset added.
Updated Figure 14 on page 24.
Added register section.
Update programming procedure in “3.5. Configuring
the Si5338” to improve robustness.
Updated Figure 9 to include the entire programming
procedure.
Added "3.2.1. Loss-of-Signal (LOS) Alarm
Detectors" on page 17 to show the location of the
LOS detector circuits.
Updated input circuit diagrams in "3.2. Input Stage"
on page 17.
Update block diagrams with new input circuit
diagrams.
2
C address now in binary.
JC
to specification tables.
Si5338
169