SI5338 SILABS [Silicon Laboratories], SI5338 Datasheet - Page 27

• Manufacturer Part Number: SI5338
• Description: I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
• Manufacturer: SILABS [Silicon Laboratories]

5. I
Configuration and operation of the Si5338 is controlled
by reading and writing to the RAM space using the I
interface. The device operates in slave mode with 7-bit
addressing
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
The I
(SDA) and a serial clock input (SCL) as shown in
Figure 20. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
recommended by the I
The 7-bit device (slave) address of the Si5338 consists
of a 6-bit fixed address plus a user-selectable LSB bit as
shown in Figure 21. The LSB bit is selectable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I
I2C_LSB pin option have a fixed 7-bit address of 70h
(111 0000) as shown in Figure 21. Other custom I
addresses are also possible. See Table 18 for details on
device ordering information with the optional I2C_LSB
pin.
Data is transferred MSB first in 8-bit words as specified
by the I
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 22. A write burst operation is also shown where
every additional data word is written using an auto-
incremented address.
I
2
C Bus
(without I2C_LSB Option)
(with I2C_LSB Option)
Slave Address
Slave Address
2
2
C bus consists of a bidirectional serial data line
C Interface
Figure 21. Si5338 I
2
Figure 20. I
C specification. A write command consists of a
V
and
DD
0/1
can
1 1 1 0 0 0 0/1
1 1 1 0 0 0
6
6
2
C and Control Signals
5
5
2
I2C_LSB
C specification.
2
4
4
C bus. Devices without the
SDA
SCL
operate
3
3
2
2
2
C Slave Address
1
1
I2C_LSB/PDEC/FDEC
0
0
0
in
OEB/PINC/FINC
I2C_LSB pin
Standard-Mode
Control
2
2
Rev. 0.6
C
C
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 23.
AC and DC electrical specifications for the SCL and
SDA pins are shown in Table 14. The timing
specifications and timing diagram for the I
compatible with the I
supported for compatibility with SMBus interfaces.
The I
3.63 V and is 3.3 V tolerant. If a bus voltage of less than
2.5 V is used, register 27[7] = 1 must be written to
maintain compatibility with the I
Write Operation – Single Byte
Read Operation – Single Byte
Read Operation - Burst (Auto Address Increment)
Write Operation - Burst (Auto Address Increment)
S
S
S
S
S
S
2
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
C bus can be operated at a bus voltage of 1.71 to
From slave to master
From master to slave
From slave to master
From master to slave
Figure 22. I
Figure 23. I
1 A
0 A Reg Addr [7:0]
1 A
0 A Reg Addr [7:0]
0 A Reg Addr [7:0]
0 A Reg Addr [7:0]
Data [7:0]
Data [7:0] A
2
C-Bus Standard. SDA timeout is
2
2
C Write Operation
C Read Operation
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
N
A P
A Data [7:0]
A Data [7:0] A Data [7:0]
A P
P
Data [7:0]
Reg Addr +1
2
C bus standard.
N
A
P
Si5338
Reg Addr +1
P
2
C bus are
A
P
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