CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet - Page 16

• Manufacturer Part Number: CY7C1480BV25-167AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 10. Identification Codes
Table 11. Boundary Scan Exit Order (2M x 36)
Document #: 001-15143 Rev. *D
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Bit #
10
12
13
14
15
16
17
18
19
20
11
Instruction
1
2
3
4
5
6
7
8
9
165-Ball ID
G1
G2
M1
M2
C1
D1
E1
D2
E2
F1
F2
K1
N1
K2
R1
R2
J1
L1
J2
L2
Code
000
001
010
100
101
011
110
111
Captures the IO ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R10
M11
M10
P11
P10
R11
N11
L11
R3
R4
R6
N6
R8
R9
P2
P6
P3
P4
P8
P9
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CY7C1482BV25, CY7C1486BV25
Description
165-Ball ID
G10
K10
H11
G11
D10
D11
C11
E10
A10
B10
L10
K11
J10
F11
E11
F10
J11
A9
B9
A8
CY7C1480BV25
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
Page 16 of 31
165-Ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
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