CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet - Page 24

• Manufacturer Part Number: CY7C1480BV25-167AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Timing for the read-write cycle is shown in
Document #: 001-15143 Rev. *D
Notes
21. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
BWE, BW
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
Q(A1)
t CL
(continued)
t CO
Q(A2)
t OEHZ
Figure
Figure 8. Read/Write Cycle Timing
t WES
t DS
D(A3)
Single WRITE
8.
A3
t DH
t WEH
[19, 21, 22]
DON’T CARE
A4
t OELZ
UNDEFINED
Q(A4)
CY7C1482BV25, CY7C1486BV25
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
CY7C1480BV25
D(A5)
A5
Back-to-Back
WRITEs
Page 24 of 31
D(A6)
A6
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