CY7C1480BV25-167BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV25-167BZXC Datasheet

CY7C1480BV25-167BZXC

Manufacturer Part Number

CY7C1480BV25-167BZXC

Description

72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1480BV25-167BZXC.pdf (34 pages)

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72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM

Features

■

Selection Guide

Note

Cypress Semiconductor Corporation

Document Number: 001-15143 Rev. *H

Maximum access time

Maximum operating current

Maximum complementary metal oxide semiconductor (CMOS)

standby current

1. For best practices recommendations, refer to the Cypress application note

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

2.5-V core power supply

2.5-V I/O operation

Fast clock-to-output time

❐

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480BV25,

JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP),

Pb-free and non Pb-free 165-ball fine-pitch ball grid array

(FBGA) package. CY7C1486BV25 available in Pb-free and

non-Pb-free 209-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

“ZZ” sleep mode option

3.0 ns (for 250 MHz device)

CY7C1482BV25

Description

•

available

198 Champion Court

Pentium

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

AN1064, SRAM System

Functional Description

The

SRAM integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

Chip Enables (CE

ADSP, and ADV), Write Enables (BW

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) is active. Subsequent burst addresses

can be internally generated as controlled by the Advance pin

(ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed Write cycle. This part supports Byte Write

operations (see

page 11

bytes wide, as controlled by the byte write control inputs. When

it is active LOW, GW writes all bytes.

250 MHz

•

450

120

3.0

for further details). Write cycles can be one to two or four

CY7C1482BV25, CY7C1486BV25

CY7C1480BV25/CY7C1482BV25/CY7C1486BV25

San Jose

Guidelines.

Pin Definitions on page 8

Pipelined Sync SRAM

200 MHz

and CE

CA 95134-1709

450

120

3.0

), Burst Control inputs (ADSC,

CY7C1480BV25

167 MHz

, and BWE), and Global

400

120

3.4

Revised May 4, 2011

•

and

), depth-expansion

Truth Table on

408-943-2600

Unit

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