CY7C1480BV25-167BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV25-167BZXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1480BV25-167BZXC
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-15143 Rev. *H
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
16. Timing reference level is 1.25 V when V
17. Test conditions shown in (a) of
18. This part has an internal voltage regulator; t
19. t
20. At any possible voltage and temperature, t
21. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
CHZ
Parameter
, t
CLZ
, t
OELZ
, and t
OEHZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to Low Z
Clock to High Z
OE LOW to output valid
OE LOW to output Low Z
OE HIGH to output High Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
DD
are specified with AC test conditions shown in part (b) of
(typical) to the first access
[16, 17]
Figure 3 on page 22
DDQ
OEHZ
[19, 20, 21]
X
X
[19, 20, 21]
POWER
= 2.5 V.
setup before CLK rise
hold after CLK rise
Description
is less than t
is the time that the power is supplied above V
unless otherwise noted.
[19, 20, 21]
[19, 20, 21]
OELZ
[18]
and t
CHZ
is less than t
Figure 3 on page
CLZ
Min
4.0
2.0
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
2.0
1.3
0.4
1
–
–
0
–
–
to eliminate bus contention between SRAMs when sharing the same data
250 MHz
CY7C1482BV25, CY7C1486BV25
DD
(minimum) initially before a read or write operation can be initiated.
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
22. Transition is measured ±200 mV from steady-state voltage.
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
0
–
200 MHz
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1480BV25
Min
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
167 MHz
Max
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 23 of 34
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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