CAT28LV64 CATALYST [Catalyst Semiconductor], CAT28LV64 Datasheet - Page 6

• Manufacturer Part Number: CAT28LV64
• Description: 64K-Bit CMOS PARALLEL E2PROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
Doc. No. 25035-00 2/98
ADDRESS
DATA OUT
DATA IN
WE
OE
CE
ADDRESS
DATA OUT
WE
OE
CE
t AS
V IH
t OES
HIGH-Z
t CS
t LZ
t AH
t RC
t CE
t OLZ
t WP
t OE
t DS
DATA VALID
HIGH-Z
6
DATA VALID
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
t OH
t DH
t CH
t OEH
t BLC
t AA
t WC
DATA VALID
t OHZ
t HZ
5096 FHD F06
28LV64 F06