CAT28LV64 CATALYST [Catalyst Semiconductor], CAT28LV64 Datasheet - Page 7

• Manufacturer Part Number: CAT28LV64
• Description: 64K-Bit CMOS PARALLEL E2PROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

Page Write
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single E
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
t
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A
to A
byte within the page is defined by address bits A
Figure 5. Byte Write Cycle [CE Controlled]
Figure 6. Page Mode Write Cycle
WP
ADDRESS
DATA OUT
ADDRESS
, and then high) the page write mode can begin by
DATA IN
12
, is latched on the last falling edge of WE. Each
WE
OE
WE
CE
OE
CE
I/O
t CS
t AS
t OES
BYTE 0
t WP
t AH
2
PROM write
t CW
BYTE 1
0
t DS
to A
DATA VALID
HIGH-Z
5
4
t BLC
BYTE 2
7
t OEH
t CH
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t
Upon completion of the page write sequence, WE must
stay high a minimum of t
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
BYTE n
t BLC
t DH
BYTE n+1
t WC
BLC MAX
BLC MAX
LAST BYTE
BYTE n+2
of the rising edge of the
for the internal auto-
t WC
Doc. No. 25035-00 2/98
BLC MAX
5094 FHD F07
5096 FHD F10
.