CAT5271ZI-00-GT3 ONSEMI [ON Semiconductor], CAT5271ZI-00-GT3 Datasheet - Page 9

• Manufacturer Part Number: CAT5271ZI-00-GT3
• Description: Dual 256-Position I2C Compatible Digital Potentiometer
• Manufacturer: ONSEMI [ON Semiconductor]

I
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5271 will be considered a slave device
in all applications.
START Condition
device, and is defined as a high to low transition of SDA
when SCL is high. The CAT5271 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
START condition. The Master then sends the address of the
particular slave device it is requesting. The seven most
significant bits of the 8−bit slave address are fixed as
0101111 for the CAT5271. The next bit (R/W) selects
between the type of the instruction Read or Write. If the bit
2
C Bus Protocol
The following defines the features of the I
The device controlling the transfer is a master, typically a
The START condition precedes all commands to the
A low to high transition of SDA when SCL is high
The bus Master begins a transmission by sending a
SDA OUT
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
SDA IN
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
SCL
t SU:STA
t F
t HD:STA
t LOW
2
C bus protocol:
t AA
Figure 15. Bus Timing Diagram
t HD:DAT
t HIGH
http://onsemi.com
t LOW
9
is logic high, then a Read instruction is performed. If the bit
is logic low, then the Write command is executed.
address byte, the CAT5271 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5271 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Write Operation
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte. After receiving another
acknowledge from the Slave, the Master device transmits
the data to be written into the wiper register. The CAT5271
acknowledges once more and the Master generates the
STOP condition.
t DH
After the Master sends a START condition and the slave
After a successful data transfer, each receiving device is
The CAT5271 responds with an acknowledge after
When the CAT5271 is in a READ mode it transmits 8 bits
In the Write mode, the Master device sends the START
t SU:DAT
t R
t SU:STO
t BUF