CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 20

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
Switching Waveforms
Notes:
30. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
31. t
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
CLKA
MBA
ENA
A
CLKB
CSB
W/RB
ENB
B
CSA
W/RA
FF/IR
EF/OR
MBB
in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
word to the output register may occur one CLKB cycle later than shown.
SKEW1
0–35
0–35
is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register
HIGH
LOW
HIGH
HIGH
LOW
LOW
FIFO Empty
(continued)
t
t
t
ENS
DS
ENS
W1
Old Data in FIFO Output Register
t
t
ENH
t
ENH
DH
t
SKEW1
[31]
t
CLKH
t
CLK
t
CLKL
t
CLKH
t
CLK
t
CLKL
t
t
A
REF
SKEW1
t
ENS
, then the transition of OR HIGH and load of the first
t
ENH
t
REF
[1, 30]
W1
CY7C43643
CY7C43663
CY7C43683
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