CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 5

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
Functional Description
The CY7C436x3 is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be output in
36-bit, 18-bit, or 9-bit formats with a choice of Big or Little
Endian configurations.
The CY7C436x3 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple unidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436x3: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. The FIFO also has two Master Reset
pins, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. The FIFO has its own independent
Partial Reset pin, PRS.
The CY7C436x3 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long-word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(nevertheless, accessing subsequent words does necessitate
a formal read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a combined Full/Input Ready flag (FF/IR). The EF and FF
functions are selected in the CY Standard Mode. EF indicates
whether the memory is full or not. The IR and OR functions are
selected in the First-Word Fall-Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates when a
selected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a
selected number of words written to the memory achieve a
predetermined “almost full state.”
selects
serial
flag
programming,
[2]
parallel
[1]
flag
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that reads data from its array. Programmable offset for AE and
AF can be loaded in parallel using Port A or in serial via the
SD input. Three default offset settings are also provided. The
AE threshold can be set at 8, 16, or 64 locations from the
empty boundary and AF threshold can be set at 8, 16, or 64
locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436x3 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Signal Description
Master Reset (MRS1, MRS2)
The FIFO memory of the CY7C436x3 undergoes a complete
reset by taking its associated Master Reset (MRS1, MRS2)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Master Reset
input can switch asynchronously to the clocks. A Master Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after power
up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS)
Each of the two FIFO memories of the CY7C436x3 undergoes
a limited reset by taking its associated Partial Reset (PRS)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset
inputs can switch asynchronously to the clocks. A Partial Rest
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or IDT Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
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