MC14538 ONSEMI [ON Semiconductor], MC14538 Datasheet - Page 8

• Manufacturer Part Number: MC14538
• Description: Dual Precision Retiggerable/Resettable Monostable Multivibrator
• Manufacturer: ONSEMI [ON Semiconductor]

TRIGGER OPERATION
Figure 1, with circuit operation following.
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor C
to V
(while inputs B and Reset are held to V
recognized, which turns on comparator C1 and N–channel
transistor N1 . At the same time the output latch is set. With
transistor N1 on, the capacitor C
V
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
C
V
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 . This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
the current through resistor R
are “off” with total device current due only to reverse
junction leakages. An added feature of the MC14538B is
that the output latch is set via the input trigger without regard
to the capacitor voltage. Thus, propagation delay from
trigger to Q is independent of the value of C
cycle of the input waveform.
X
SS
DD
The block diagram of the MC14538B is shown in
As shown in Figure 1 and 10, before an input trigger
In the quiescent state, C
RESET
C
begins to charge through the timing resistor, R
DD
. When the voltage across C
X
until V
/R
Q
A
B
X
. When the trigger input A goes from V
ref1
V
is reached. At this point the output of
ref 1
1
X
T
V
is fully charged to V
ref 2
X
1
2
3
to be zero. Both comparators
X
X
Positive edge trigger
Negative edge trigger
Positive edge trigger
rapidly discharges toward
equals V
X
V
DD
ref 1
completely charged
) a valid trigger is
2
X
ref 2
, R
X
, comparator
Figure 10. Timing Operation
THEORY OF OPERATION
, or the duty
DD
SS
T
X
V
, toward
to V
causing
ref 2
http://onsemi.com
MC14538B
DD
4
5
8
Positive edge re–trigger (pulse lengthening)
Positive edge re–trigger (pulse lengthening)
V
ref 1
RETRIGGER OPERATION
followed by another valid trigger
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
V
in output pulse width T. When a valid retrigger is initiated
progressing along the RC charging curve toward V
Q output will remain high until time T, after the last valid
retrigger.
RESET OPERATION
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to V
voltage on the capacitor reaches V
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level
is detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width
specification.
ref 1
, the voltage at C
The MC14538B is retriggered if a valid trigger occurs
The MC14538B may be reset during the generation of the
3
, but has not yet reached V
4
DD
T
V
ref 2
by turning on transistor P1 . When the
X
/R
X
will again drop to V
V
ref 1
ref 2
V
ref 2
ref 2
before the Q output has
, will cause an increase
5
, the reset latch will
ref 1
DD
before
. The