CAT93C57 CATALYST [Catalyst Semiconductor], CAT93C57 Datasheet - Page 5

• Manufacturer Part Number: CAT93C57
• Description: 2-Kb Microwire Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

POWER-UP TIMING
Notes
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
(2) t
A.C. Test Conditions
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C56/57 can be organized as
either registers of 16 bits or 8 bits. When organized as
X16, seven 10-bit instructions for 93C57 or seven 11-
bit instructions for 93C56 control the reading, writing
and erase operations of the device. When organized
as X8, seven 11-bit instructions for 93C57 or seven
12-bit instructions for 93C56 control the reading,
writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and
will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
Figure 1. Sychronous Data Timing
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
Symbol
AEC-Q100 and JEDEC test methods.
PUR
:
t
t
PUW
PUR
DO
SK
CS
and t
DI
PUW
are the delays required from the time V
Parameter
Power-up to Read Operation
Power-up to Write Operation
(1) (2)
t CSS
0.4V to 2.4V
0.8V, 2.0V
Current Source I
≤
0.2V
0.5V
VALID
50 ns
t DIS
CC
CC
to 0.7V
t SKHI
CC
CC
is stable until the specified operation can be initiated.
OLmax
4.5V ≤ V
4.5V ≤ V
1.8V ≤ V
1.8V ≤ V
/I
t DIS
t SKLOW
OHmax
5
Max
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
; CL=100pF
1
1
CC
CC
CC
CC
VALID
≤ 5.5V
≤ 5.5V
≤ 4.5V
≤ 4.5V
Units
ms
ms
t DIH
t PD0, t PD1
DATA VALID
t CSH
CAT93C56, CAT93C57
t CSMIN
Doc. No. MD-1088 Rev. P