CAT93C57 CATALYST [Catalyst Semiconductor], CAT93C57 Datasheet - Page 9

• Manufacturer Part Number: CAT93C57
• Description: 2-Kb Microwire Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
t
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C56/57 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Figure 6. ERAL Instruction Timing
Figure 7. WRAL Instruction Timing
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CSMIN
DO
SK
CS
DI
DO
. The falling edge of CS will start the self clocking
CS
SK
DI
1
1
0
0
HIGH-Z
0
0
0
1
1
0
9
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C56/57 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
CSMIN
D N
(Figure 7). The falling edge of CS will start the
t SV
D 0
t EW
STATUS VERIFY
t CS
BUSY
t SV
t EW
READY
STATUS VERIFY
t CSMIN
BUSY
CAT93C56, CAT93C57
READY
t HZ
STANDBY
HIGH-Z
Doc. No. MD-1088 Rev. P
STANDBY
HIGH-Z
t HZ