MC74VHC1GT126DF2 ONSEMI [ON Semiconductor], MC74VHC1GT126DF2 Datasheet

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MC74VHC1GT126DF2

Manufacturer Part Number
MC74VHC1GT126DF2
Description
Noninverting Buffer / CMOS Logic Level Shifter
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet
MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
set Low to place the output into the high impedance state.
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when V
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
December, 2003 − Rev. 9
The MC74VHC1GT126 is a single gate noninverting 3−state buffer
The MC74VHC1GT126 requires the 3−state control input (OE) to be
The device input is compatible with TTL−type input thresholds and the
The MC74VHC1GT126 input structure provides protection when
CMOS−Compatible Outputs: V
High Speed: t
Low Power Dissipation: I
TTL−Compatible Inputs: V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent Gates = 16
Semiconductor Components Industries, LLC, 2002
PD
IN A
OE
= 3.5 ns (Typ) at V
GND
Figure 1. Pinout (Top View)
IN A
OE
Figure 2. Logic Symbol
1
2
3
CC
IL
= 1 mA (Max) at T
= 0.8 V; V
OH
> 0.8 V
CC
= 5 V
5
4
IH
CC
V
OUT Y
= 2.0 V
CC
; V
OUT Y
OL
A
= 25 C
< 0.1 V
CC
CC
1
@Load
= 0 V.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
A Input
1
2
4
3
5
H
X
L
SC−88A / SOT−353/SC−70
ORDERING INFORMATION
TSOP−5/SOT−23/SC−59
FUNCTION TABLE
http://onsemi.com
PIN ASSIGNMENT
CASE 419A
DF SUFFIX
DT SUFFIX
CASE 483
OE Input
H
H
L
Publication Order Number:
OUT Y
GND
MC74VHC1GT126/D
IN A
V
OE
CC
DIAGRAMS
Pin 1
d = Date Code
Pin 1
d = Date Code
MARKING
Y Output
W3
W3
H
Z
L
d
d

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MC74VHC1GT126DF2 Summary of contents

Page 1

MC74VHC1GT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHC1GT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS ...

Page 2

MAXIMUM RATINGS (Note 1) Symbol V DC Supply Voltage Input Voltage Output Voltage OUT I Input Diode Current IK I Output Diode Current Output Current, per Pin OUT I DC Supply ...

Page 3

DC ELECTRICAL CHARACTERISTICS Î Î Î Î ...

Page 4

... Figure 6. Test Circuit DEVICE ORDERING INFORMATION Temp Circuit Range Device Indicator Identifier Order Number MC74VHC1GT126DF1 MC MC74VHC1GT126DF2 MC MC74VHC1GT126DT1 MC †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC74VHC1GT126 SWITCHING WAVEFORMS ...

Page 5

TAPE TRAILER (Connected to Reel Hub) CAVITY TOP TAPE NO COMPONENTS TAPE 160 mm MIN TAPE DIMENSIONS mm 4.00 2.00 8.00 $0.30 Figure 10. SC−70−5/SC−88A/SOT−353 DF1 Reel Configuration/Orientation TAPE DIMENSIONS mm 4.00 2.00 8.00 $0.30 Figure 11. SC−70/SC−88A/SOT−353 DF2 and ...

Page 6

MC74VHC1GT126 1.5 mm MIN 20.2 mm MIN A (0.795 in) FULL RADIUS Figure 12. Reel Dimensions REEL DIMENSIONS Tape Size T and R Suffix A Max 178 mm (7 in) DIRECTION OF FEED Figure 13. Reel ...

Page 7

−B− 0.2 (0.008 0.50 0.0197 0.40 0.0157 Figure 14. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting ...

Page 8

0.05 (0.002) H Figure 15. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and ...

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