HSP48410/883 INTERSIL [Intersil Corporation], HSP48410/883 Datasheet - Page 3

• Manufacturer Part Number: HSP48410/883
• Description: Histogrammer/Accumulating Buffer
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Description
CLK
PIN0-9
LD
FCT0-2
START
FC
DIN0-23
DIO0-23
IOADD0-9
UWS
WR
RD
V
GND
CC
SYMBOL
C6
A1-5, A7, B3-5, C5
C1
D1-2, E3
B1
B2
A8-11, B6-11,
C10-11, D10-11,
E9-11, F10-11,
G9-11, H10-11
J5-7, J10-11,
K2-11, L2-4, L6-11
F1, F3, G1-3, H1-2,
J1-2, K1
F2
E2
C2
A6, L1
C7, E1, F9, L5
PIN NUMBER
3
TYPE
I/O
I
I
I
I
I
I
I
I
I
I
I
HSP48410/883
Clock Input. This input has no effect on the chips functionality when the chip is
programmed to an asynchronous mode. All signals denoted as synchronous have
their timing specified with reference to this signal.
Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on
chip RAM with address values in Histogram, Bin Accumulate and LUT (write) mode.
During Asynchronous modes it is unused.
The Load pin is used to load the FCT0-2 bits into the FCT Registers.
(See below).
These three pins are decoded to determine the mode of operation for the chip. The
signals are sampled by the rising edge of LD and take effect after the rising edge of
LD. Since the loading of this function is asynchronous to CLK, it is necessary to
disable the START pin during loading and enable START at least 1 CLK cycle
following the LD pulse.
This pin informs the on chip circuitry which clock cycle will start and/or stop the
current mode of operation. Thus, the modes are asynchronously selected (via LD)
but are synchronously started and stopped. This input is sampled by the rising edge
of CLK. The actual function of this input depends on the mode that is selected.
START must always be held high (disabled) when changing modes. This will provide
a smooth transition from one mode to the next by allowing the part to reconfigure
itself before new mode begins. When START is high, LUT (read) mode is enabled
except for Delay and Subtract Modes.
Flash Clear. This input provides a fully asynchronous signal which effectively resets
all bits in the RAM Array and the input and output data paths to zero.
Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT,
Delay and Delay and Subtract Modes. Synchronous to CLK.
Asynchronous Data Bus. Provides RAM access for a microprocessor in
preconditioning the memory array and reading the results of the previous operation.
Configurable as either a 24-bit or 16-bit bus.
RAM Address in Asynchronous Modes. Sampled on the falling edge of WR or RD.
Upper Word Select. In 16-bit asynchronous mode, a one on this pin denotes the
contents of DIO0-7 as being the upper eight-bits of the data in or out of the
Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes,
this pin has no effect.
Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured
in one of the asynchronous modes. Asynchronous to CLK.
Read control for the data on DIO0-23 in asynchronous modes. Output enable for
DIO0-23 in other modes. Asynchronous to CLK.
+5V.
Ground.
DESCRIPTION