AD8324ACP-EVAL AD [Analog Devices], AD8324ACP-EVAL Datasheet - Page 11

• Manufacturer Part Number: AD8324ACP-EVAL
• Description: 3.3 V Upstream Cable Line Driver
• Manufacturer: AD [Analog Devices]

Table 6. Adjacent Channel Power
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
POWER SUPPLY
The 3.3 V supply should be delivered to each of the V
a low impedance power bus. This ensures that each pin is at the
same potential. The power bus should be decoupled to ground
using a 10 µF tantalum capacitor located close to the AD8324.
In addition to the 10 µF capacitor, V
to ground with ceramic chip capacitors located close to the pins.
The bypass pin, labeled BYP, should also be decoupled. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8324 and the
output transformer. All AD8324 ground pins must be connected
to the ground plane to ensure proper grounding of all internal
nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance, which
is most critical between the outputs of the AD8324 and the 1:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
Z
IN
= 150Ω
DATEN
SDATA
SLEEP
V
V
TXEN
IN+
CLK
IN–
V
CC
CC
0.1µF
174Ω
0.1µF
pins should be decoupled
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
10µF
160
–63
–63
–64
–67
–70
–72
10
1
2
3
4
5
6
7
8
9
CC
Figure 23. Typical Application Circuit
GND
GND
GND
V
V
GND
DATEN
SDATA
CLK
V
pins via
CC
IN+
IN–
AD8324-JRQ
Rev. 0 | Page 11 of 16
320
–64
–64
–64
–65
–67
–70
Adjacent Channel Symbol Rate (kSym/s)
SLEEP
RAMP
V
V
TXEN
OUT+
GND
OUT–
GND
BYP
V
NC
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guide-
lines will optimize the overall performance of the AD8324 in all
applications.
INITIAL POWER-UP
When the supply voltage is first applied to the AD8324, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the Gain
Programming for the AD8324 section. The TXEN pin can then
be brought from Logic 0 to Logic 1, enabling forward signal
transmission at the desired gain level.
RAMP PIN AND BYP PIN FEATURES
The RAMP pin (Pin 15) is used to control the length of the
burst on and off transients. By default, leaving the RAMP pin
unconnected will result in a transient that is fully compliant
with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During
Burst On/Off Transients. DOCSIS requires that all between
burst transients must be dissipated no faster than 2 µs. Adding
capacitance to the RAMP pin will slow the dissipation even
more.
CC
640
–68
–66
–65
–65
–66
–67
20
19
18
17
16
15
14
13
12
11
0.1µF
0.1µF
1280
–71
–70
–67
–66
–66
–67
1:1
TOKO 458PT-1556
TO DIPLEXER
Z
2560
–72
–72
–71
–68
–67
–64
IN
= 75Ω
5120
–66
–67
–67
–67
–65
–64
AD8324