AD8324ACP-EVAL AD [Analog Devices], AD8324ACP-EVAL Datasheet - Page 4

• Manufacturer Part Number: AD8324ACP-EVAL
• Description: 3.3 V Upstream Cable Line Driver
• Manufacturer: AD [Analog Devices]

AD8324
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2
3
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LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC)
Table 2. DATEN , CLK, SDATA, TXEN, SLEEP , V
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
Logic 1 Current (V
Logic 0 Current (V
TIMING REQUIREMENTS
Table 3. V
Parameter
Clock Pulse Width (t
Clock Period (t
Setup Time SDATA vs. Clock (t
Setup Time DATEN vs. Clock (t
Hold Time SDATA vs. Clock (t
Hold Time DATEN vs. Clock (t
Input Rise and Fall Times, SDATA, DATEN , Clock (t
ANALOG
OUTPUT
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz.
V
Guaranteed by design and characterization to ±6 sigma for T
Guaranteed by design and characterization to ±3 sigma for T
Measured through a 1:1 transformer.
Specification is worst case over all gain codes.
SDATA
DATEN
TXEN
IN
CLK
= 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
t
DS
SIGNAL AMPLITUDE (p-p)
CC
= 3.3 V, t
t
ES
t
VALID DATA WORD G1
VUH
C
8 CLOCK CYCLES
)
MSB . . . LSB
INH
INL
INH
INL
INH
INL
Figure 3. Serial Interface Timing
WH
t
= 0 V), CLK, SDATA, DATEN
= 0 V), TXEN
= 0 V), SLEEP
C
= 3.3 V), CLK, SDATA, DATEN
= 3.3 V), TXEN
= 3.3 V), SLEEP
R
)
= t
t
EH
F
= 4 ns, f
GAIN TRANSFER (G1)
DH
EH
t
GS
DS
ES
)
)
)
)
CLK
t
OFF
VALID DATA WORD G2
= 8 MHz, unless otherwise noted
R
, t
CC
t
F
A
A
CN
)
GAIN TRANSFER (G2)
= 25°C.
= 25°C.
= 3.3 V, unless otherwise noted
Rev. 0 | Page 4 of 16
SDATA
CLK
MSB
Min
16.0
32.0
5.0
15.0
5.0
3.0
Min
2.1
0
0
−600
50
−250
50
−250
t
DS
Figure 4. SDATA Timng
VALID DATA BIT
MSB-1
Typ
Typ
t
DH
Max
10
Max
3.3
0.8
20
−100
190
−30
190
−30
MSB-2
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
V
V
nA
nA
µA
µA
µA
µA