AD8332 AD [Analog Devices], AD8332 Datasheet - Page 22

• Manufacturer Part Number: AD8332
• Description: Ultralow Noise VGAs with Preamplifier and Programmable RIN
• Manufacturer: AD [Analog Devices]

AD8331/AD8332
APPLICATIONS
LNA – EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be
bypassed to ground, and signal source to the INH pin
capacitively coupled using 2.2 nF to 0.1 μF capacitors (see
Figure 66).
The unterminated input impedance of the LNA is 6 kΩ. The
user may synthesize any LNA input resistance between 50 Ω
and 6 kΩ. R
from Table .
Table 3. LNA External Component Values
for Common Source Impedances
R
50
75
100
200
500
6k
When active input termination is used, a 0.1 µF capacitor (C
required to isolate the input and output bias voltages of the LNA.
The shunt input capacitor, C
frequencies where the active termination match is lost due to
the HF gain roll-off of the LNA. Suggested values are shown in
Table ; for unterminated applications, reduce the capacitor value
by half.
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values may prove useful.
Figure 67 shows the interconnection details of the LNA output.
Capacitive coupling between LNA outputs and the VGA inputs
is required because of differences in their dc levels and to
eliminate the offset of the LNA. Capacitor values of 0.1 µF are
recommended. There is 0.4 dB loss in gain between the LNA
output and the VGA input due to the 5 Ω output resistance.
Additional loading at the LOP and LON outputs will affect
LNA gain.
IN
(Ω)
R
280
412
562
1.13k
3.01k
∞
FB
FB
(Nearest STD 1% Value, Ω)
is calculated according to Equation 6 or selected
R
FB
=
33
6
k
SH
k
Ω
Ω
, reduces gain peaking at higher
–
×
( )
R
( )
R
IN
IN
( )
6
C
22
12
8
1.2
None
None
SH
(pF)
FB
) is
Rev. C | Page 22 of 32
0.1µF
Both LNA outputs are available for driving external circuits. Pin
LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it will tolerate a load capacitance
up to 100 pF with the addition of a 49.9 Ω series resistor or
ferrite 75 Ω/100 MHz bead.
V
GAIN
Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)
0.1µF
1nF
1nF
C
SH
1nF
Figure 67. Interconnections of the LNA and VGA
+5V
10
11
12
13
14
3
6
8
1
2
4
5
7
9
LMD2
INH2
VPS2
LON2
LOP2
COM2
VIP2
VIN2
VCM2
GAIN
RCLMP
VOH2
VOL2
COMM
LNA
*
SEE TEXT
C
0.1µF
LMD
COM1
LMD1
VCM1
VOH1
LON1
LOP1
VOL1
VPSV
VPS1
HILO
INH1
VIP1
VIN1
ENB
5Ω
5Ω
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1nF
LON
LOP
*
*
5V
0.1µF
5V
R
C
1nF
FB
FB
0.1µF
*
*
VGA OUT
VGA OUT
FB
LNA OUT
C
VIP
VCM
SH
1n F
VIN
5V
*
0.1µF
50Ω
50Ω
5V
0.1µF
0.1 F
CIRCUIT
TO EXT
CIRCUIT
TO EXT
100Ω
100Ω
SOURCE
LNA