PCF2113AU/10/F4 NXP [NXP Semiconductors], PCF2113AU/10/F4 Datasheet - Page 25
PCF2113AU/10/F4
Manufacturer Part Number
PCF2113AU/10/F4
Description
LCD controllers/drivers
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF2113AU10F4.pdf
(65 pages)
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NXP Semiconductors
Table 10.
PCF2113_FAM_4
Product data sheet
Instruction
H = 0 or 1 (basic and extended functions)
NOP
Function set
Read busy flag
and address
counter
Read data
Write data
H = 0 (basic functions)
Clear display
Return home
Instruction set with parallel bus commands
Control and command bits
RS
0
0
0
1
1
0
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
0
0
0
There are 4 types of instructions:
In normal use, data transfer instructions are used most frequently. However, automatic
incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write
lessens the microcontroller program load. The display shift in particular can be performed
concurrently with display data write, enabling the designer to develop systems in minimum
time with maximum programming efficiency.
During internal operation, no instructions other than the ‘read busy flag’ and ‘read
address’ instructions will be executed. Because the busy flag is set to logic 1 while an
instruction is being executed, check to ensure it is logic 0 before sending the next
instruction or wait for the maximum instruction execution time, as given in
instruction sent while the busy flag is logic 1 will not be executed.
•
•
•
•
Designate PCF2113x functions such as display format, data length
Set internal RAM addresses
Perform data transfer with internal RAM
Other functions
0
0
BF
read data
write data
0
0
0
0
AC
0
0
0
1
0
0
0
DL
0
0
Rev. 04 — 4 March 2008
0
0
0
0
0
M
0
0
0
SL
0
1
0
H
1
0
Description
no operation
sets interface Data
Length (DL), number of
display lines (M), single
line/MUX 1:9 (SL) and
extended instruction set
control (H)
reads the Busy Flag (BF),
indicating internal operating
is being performed, and the
Address Counter (AC)
reads data from CGRAM or
DDRAM
writes data to CGRAM or
DDRAM
clears entire display and sets
DDRAM address 0 in
address counter
sets DDRAM address 0 in
address counter; also
returns shifted display to
original position; DDRAM
contents remain unchanged
[1]
LCD controllers/drivers
PCF2113x
© NXP B.V. 2008. All rights reserved.
Table
Required
clock
cycles
3
3
0
3
3
165
3
10. An
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