PCF2119AU/2DA/2 NXP [NXP Semiconductors], PCF2119AU/2DA/2 Datasheet - Page 41

• Manufacturer Part Number: PCF2119AU/2DA/2
• Description: LCD controllers/drivers
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF2119X_5
Product data sheet
11.2 I
The I
The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
2
Fig 26. System configuration
Fig 27. Bit transfer
Fig 28. Definition of START and STOP conditions
C-bus interface
2
SCL
SDA
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
SDA
SCL
S
Rev. 05 — 13 August 2009
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
SLAVE
change
allowed
of data
TRANSMITTER
MASTER
STOP condition
LCD controllers/drivers
mbc621
P
PCF2119x
TRANSMITTER/
© NXP B.V. 2009. All rights reserved.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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