PCF2127AT/1 NXP [NXP Semiconductors], PCF2127AT/1 Datasheet - Page 26
PCF2127AT/1
Manufacturer Part Number
PCF2127AT/1
Description
Integrated RTC, TCXO and quartz crystal
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF2127AT1.pdf
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NXP Semiconductors
PCF2127A_2
Product data sheet
8.8.1 Power-On Reset (POR)
8.8.2 Power-On Reset Override (PORO)
8.8 Reset function
The PCF2127A has an active LOW open-drain output reset pin (RST). The reset output is
activated at Power-On Reset (POR) and whenever the oscillator is stopped (see
Section
The POR is active whenever the oscillator is stopped. The oscillator is also considered to
be stopped during the time between power-on and stable crystal resonance (see
Figure
supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set
logic 1).
After POR, the following mode is entered:
The register values after power-on are shown in
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and therefore speed up on-board test of the device.
Fig 14. Dependency between POR and oscillator
•
•
•
•
•
•
32.768 kHz CLKOUT active
Power-On Reset Override (PORO) available to be set
24 hour mode is selected
Battery switch-over is enabled
Battery low detection is enabled
Extra power fail detection is enabled
14). This time may be in the range of 200 ms to 2 s depending on temperature and
8.7).
oscillation
V
RST
DD
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 May 2010
chip in reset
Integrated RTC, TCXO and quartz crystal
Table
4.
chip not in reset
PCF2127A
© NXP B.V. 2010. All rights reserved.
013aaa243
t
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