PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 14

• Manufacturer Part Number: PCF8531U
• Description: 34 x 128 pixel matrix driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531_4
Product data sheet
7.11 V
7.12 Reset
7.13 Power-down
7.14 Column driver outputs
7.15 Row driver outputs
The V
programmed by software.
The PCF8531 has the possibility of two reset modes: internal power-on reset or external
reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has
the following state:
During power-down, all static currents are switched off (no internal oscillator, no timing
and no LCD segment drive system) and all LCD outputs are internally connected to V
The I
The LCD drive section includes 128 column outputs (C0 to C127) which must be
connected directly to the LCD. The column output signals are generated in accordance
with the multiplexed row signals and with the data in the display latch. When less than
128 columns are required, the unused column outputs must be left open-circuit.
The LCD drive section includes 34 row outputs (R0 to R33), which must be connected
directly to the LCD. The row output signals are generated in accordance with the selected
LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused
outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is
R0, R2, ..., R1, R3, etc.
•
•
•
•
LCD
Power save mode: 3.0 V to 9.0 V.
All row and column outputs are set to V
RAM data is undefined
Power-down mode
2
LCD
C-bus function remains operational.
generator
voltage generator contains a configurable 2 to 5 times voltage multiplier; this is
Rev. 04 — 13 June 2008
SS
(display off)
34 x 128 pixel matrix driver
PCF8531
© NXP B.V. 2008. All rights reserved.
14 of 44
SS
.