PCF85321 NXP [NXP Semiconductors], PCF85321 Datasheet - Page 5

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PCF85321

Manufacturer Part Number
PCF85321
Description
Universal LCD driver for low multiplex rates
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PCF8532_1
Product data sheet
7.1 Power-on reset
7.2 LCD bias generator
The host microprocessor or microcontroller maintains the 2-line I
channel with the PCF8532.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V
power supplies (V
At power-on the PCF8532 resets to a default starting condition:
Do not transfer data on the I
action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
series resistors connected between V
out of the circuit to provide a
Fig 3.
All backplane and segment outputs are set to V
The selected drive mode is 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled
If internal oscillator is selected (OSC pin connected to V
signal on pin CLK
V
V
DD
SS
CONTROLLER
2
PROCESSOR/
Typical system configuration
C-bus interface is initialized
MICRO-
MICRO-
HOST
SS
. The only other connections required to complete the system are the
R
DD
2C
t
, V
r
B
Rev. 1 — 10 February 2009
SS
and V
2
C-bus after a power-on for at least 1 ms to allow the reset
1
2
SDAACK
bias voltage level for the 1:2 multiplex configuration.
LCD
OSC
SDA
SCL
) and the LCD panel selected for the application.
LCD
and V
A0
Universal LCD driver for low multiplex rates
PCF8532
V
DD
A1 SA0
SS
V
1
. The center resistor can be switched
LCD
3
LCD
bias
V
SS
160 segment drives
4 backplanes
SS
), then there is no clock
2
C-bus communication
PCF8532
© NXP B.V. 2009. All rights reserved.
LCD PANEL
(up to 640
elements)
001aah852
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