M41ST85W_11 STMICROELECTRONICS [STMicroelectronics], M41ST85W_11 Datasheet - Page 32

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M41ST85W_11

Manufacturer Part Number
M41ST85W_11
Description
3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
DC and AC parameters
Figure 19. Bus timing requirements sequence
Table 12.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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t
Symbol
HD:DAT
t
t
t
t
SU:STO
HD:STA
SU:DAT
SU:STA
t
t
t
f
t
EXPD
HIGH
LOW
SCL
BUF
t
t
R
F
(2)
SDA
SCL
SCL clock frequency
Time the bus must be free before a new transmission can start
EX to E
SDA and SCL fall time
Data hold time
START condition hold time (after this period the first clock pulse is generated)
Clock high period
Clock low period
SDA and SCL rise time
Data setup time
START condition setup time (only relevant for a repeated start condition)
STOP condition setup time
AC characteristics
tBUF
CON
P
propagation delay
S
tHD:STA
tR
A
= –40 to 85°C; V
Parameter
tLOW
Doc ID 7531 Rev 11
tHIGH
tF
CC
(1)
= 2.7 to 3.6 V (except where otherwise noted).
tHD:DAT
tSU:DAT
SR
tSU:STA
tHD:STA
Min
600
600
100
600
600
1.3
1.3
0
0
P
AI00589
M41ST85W
tSU:STO
Max
400
300
300
15
Unit
kHz
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns

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