M41ST95WMH6TR STMICROELECTRONICS [STMicroelectronics], M41ST95WMH6TR Datasheet - Page 14

• Manufacturer Part Number: M41ST95WMH6TR
• Description: 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41ST95Y*, M41ST95W
Figure 13. WRITE Mode Sequence
Data Retention Mode
With valid V
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST95Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when
V
hibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will re-
main active until V
ternal RAM access is inhibited in a similar manner
by forcing E
0.2 volts of the V
as long as V
dition. When V
Switchover Voltage (V
from the V
the clock registers and external SRAM are main-
tained from the attached battery supply.
All outputs become high impedance. The V
is capable of supplying 100 µA of current to the at-
tached memory with less than 0.3 volts drop under
this condition. On power up, when V
a nominal value, write protection continues for
t
mains active during this time (see
21., page
Note: Most low power SRAMs on the market to-
day can be used with the M41ST95Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use.
14/35
REC
PFD
E
SCL
SDO
(min). This is accomplished by internally in-
by inhibiting E
SDI
W/R BIT
V
CC
28).
CC
CON
CC
CC
pin to the SNAPHAT
falls
CC
remains at an out-of-tolerance con-
applied, the M41ST95Y/W can be
to a high level. This level is within
BAT
MSB
CC
falls below the Battery Back-up
7
0
CON
. E
returns to nominal levels. Ex-
between
6
SO
1
CON
. The RST signal also re-
), power input is switched
5
2
7 BIT ADDR
will remain at this level
4
3
3
V
4
PFD
2
®
5
CC
(max)
battery, and
1
6
returns to
0
7
OUT
Figure
MSB
7
8
and
pin
6
HIGH IMPEDANCE
9
5
10
DATA BYTE
4
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M41ST95Y/W
and SRAMs to be “Don’t Care” once V
low V
data retention down to V
enable access time must be sufficient to meet the
system needs with the chip enable output propa-
gation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to V
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the I
the M41ST95Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT
can then be divided by this current to determine
the amount of data retention available (see 20).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
3
PFD
2
OUT
(min). The SRAM should also guarantee
1
.
0
15
7
CC
= 2.0 volts. The chip
®
of your choice
BAT
CC
AI04636
falls be-
value of