CDP68HC68T1W INTERSIL [Intersil Corporation], CDP68HC68T1W Datasheet - Page 10

• Manufacturer Part Number: CDP68HC68T1W
• Description: CMOS Serial Real-Time Clock With RAM and Power Sense/Control
• Manufacturer: INTERSIL [Intersil Corporation]

NOTES:
V
This input is connected to the system voltage. After the CPU
initiates power down by setting bit 6 in the Interrupt Control
Register to “1”, the level on this pin will terminate power
down if it rises about 0.7V above the level at the V
pin after previously falling below V
down is terminated, the PSE pin will return high and the
Clock Output will be enabled. The CPUR output pin will also
return high. The logic level present at this pin at the end of
POR determines the CDP68HC68T1’s operating mode.
V
The oscillator power source. The positive terminal of the bat-
tery should be connected to this pin. When the level on the
V
internally connected to the V
V
the connection from V
the “LINE” input is used as the frequency source, V
be tied to V
V
IN” pin can be tied to V
XTAL IN, XTAL OUT
These pins are connected to a 32,768Hz. 1.048576MHz,
2.097152MHz or 4.194304MHz crystal. If an external clock
is used, it should be connected to “XTAL IN” with ‘XTAL
OUT” left open.
V
The positive power-supply pin.
CLOCK CONTROL REGISTER (Write/Read) - Address 31H
7. All frequencies recommended oscillator circuit. C1, C2 values
8. R used for 32KHz operation only. 100K - 300K range as specified
SYS
BATT
SYS
SYS
BATT
DD
crystal dependent.
by crystal manufacturer.
START
STOP
rises a threshold above (0.7V) the voltage on V
D7
pin falls below V
is at V
DD
FIGURE 7. OSCILLATOR CIRCUIT
SS
T1
or V
XTAL
XTAL
. If V
OUT
IN
SS
XTAL
LINE
D6
BATT
BATT
. The “XTAL IN” pin must be at V
SS
22M
BATT
or V
is connected to V
to the V
DD
+0.7V, the V
DD
C2
.
pin. When the voltage on
BATT
DD
XTAL
SEL
D5
1
10 - 40pF
pin is opened. When
5 - 30pF
+0.7V. When power
C1
BATT
DD
, the “XTAL
pin will be
BATT
BATT
CDP68HC68T1
XTAL
SEL
D4
0
BATT
input
SS
may
if
,
10
Clock Control Register
START-STOP
A high written into this bit will enable the counter stages of
the clock circuitry. A low will hold all bits reset in the divider
chain from 32Hz to 1Hz. A clock out selected by bits 0, 1 and
2 will not be affected by the stop function except the 1Hz and
2Hz outputs.
LlNE-XTAL
When this bit is set high, clock operation will use the 50 or
60-cycle input present at the LINE input pin. When the bit is
low, the crystal input will generate the 1Hz time update.
XTAL Select
One of 4 possible crystals is selected by value in these two
bits:
50-60Hz
50Hz is selected as the line input frequency when this bit is
set high. A low will select 60Hz. The power-sense bit in the
Interrupt Control Register must be set low for line frequency
operation.
Clock Out
The three bits specify one of the 7 frequencies to be used as
the squarewave clock output:
All bits are reset by a power-on reset. Therefore, the XTAL is
selected as the clock output at this time.
Interrupt Control Register
Watchdog
When this bit is set high, the watchdog operation will be
enabled. This function requires the CPU to toggle the CE pin
periodically without a serial-transfer requirement. In the
event this does not occur, a CPU reset will be issued. Status
Register must be read before re-enabling watchdog.
Power Down
A high in this location will initiate a power down. A CPU reset
will occur, the CLK OUT and PSE output pins will be set low
and the serial interface will be disabled.
50Hz
60Hz
D3
0 = 4.194304MHz
1 = 2.097152MHz
0 = XTAL
1 = XTAL/2
2 = XTAL/4
3 = XTAL/8
CLK OUT
D2
2
2 = 1.048576MHz
3 = 32,768Hz
4 = Disable (low output)
5 = 1Hz
6 = 2Hz
7 = 50Hz or 60Hz
XTAL Operation = 64Hz
CLK OUT
D1
1
CLK OUT
D0
0