DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 16

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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PROPAGATION DELAY
Once the deserializer is locked, the amount of time it takes for
a signal to travel from the high speed CML serial input through
the device and out via the DDR LVDS interface is defined to
be the propagation delay. The propagation delay through the
DS32EL0124/DS32ELX0124 due to the analog circuitry is
considered negligible compared to the time delay caused by
the digital components. The information presented in this sec-
tion allows system designers to predict the propagation delay
through the device in terms of clock cycles which are propor-
tional to the high speed serial line rate.
Each clock cycle shown
the high speed serial bit rate. For example, at a serial line rate
PROPAGATION DELAY FOR RETIMED LOOP THROUGH
DRIVER — DS32ELX0124 ONLY
If the loop through driver is enabled in the DS32ELX0124, the
propagation delay can also be defined as the amount of time
it takes a signal to pass from the high speed CML serial input
to the retimed loop through driver output. This time delay is
inFigure 11
is defined to be 1/20
FIGURE 11. Deserializer Propagation Delay
FIGURE 10. SMBus Configuration 3
th
of
16
of 3.125 Gbps the clock frequency of each delay cycle would
be 156.25 MHz. Note, this is not the same frequency as the
LVDS outputs, which would be 312.5 MHz for a serial line rate
of 3.125 Gbps. Dashed lines in
feature is disabled by default in that mode and therefore add
no more time to the total propagation delay. In the last row,
bypassed indicates that the data is sampled even though the
feature is disabled by default. The sampling of the data results
in an added amount of propagation delay as specified in the
box.
measured in CDR clock cycles. The CDR clock frequency is
equal to high speed serial line rate or one high speed serial
bit width. For example, if the high speed serial line rate is
3.125 Gbps, then the CDR clock frequency is 3.125 GHz. The
propagation delay from the high speed input to the loop
through driver output is 1 CDR clock.
Figure 11
indicate that the
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