DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 7
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DS32EL0124SQ
Manufacturer Part Number
DS32EL0124SQ
Description
125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DS32EL0124SQ.pdf
(28 pages)
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V
ΔV
V
ΔV
I
t
t
t
t
t
t
t
t
t
t
t
t
OS
ROTR
ROTF
ROCP
RODC
RBIT
ROSC
ROHC
RODJ
RORJ
ROTJ
RLA
LVSK
Symbol
Symbol
OD
OS
LVDS Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
LVDS Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
OD
OS
Differential Output Voltage
Changes in V
states
Offset Voltage
Change in V
Output Short Circuit Current
LVDS low-to-high transition time
LVDS high-to-low transition time
LVDS output clock period
RxCLKOUT Duty Cycle
LVDS output bit width
RxOUT Setup to RxCLKOUT OUT
RxOUT Hold to RxCLKOUT OUT
LVDS Output Deterministic Jitter
LVDS Output Random Jitter
Peak-to-Peak LVDS Output Jitter
Deserializer Lock Time
LVDS Output Skew
OS
OD
between complimentary states
between complimentary output
Parameter
Parameter
R
V
(Note
RxCLKOUT
(Note
RxOUT0–4
(Note
RxCLKOUT
(Note
RxOUT0–4
(Note
RxCLKOUT
(Note
RxOUT0–4
(Note
(Note
1.25 Gbps
2.5 Gbps
3.125 Gbps
LVDS Differential Output Skew
between + and - pins
OUT
L
= 100Ω
7
= 0V, R
6)
3)
3)
3)
3)
3)
3)
3)
Conditions
Conditions
L
= 100Ω
(Note
(Note
2,
2,
650
650
1.125
Note
Note
Min
230
Min
-50
45
5)
5)
1.25
Typ
Typ
300
300
800
800
115
2.5
2.5
2T
50
18
43
51
70
22
90
20
T
1.375
Max
Max
www.national.com
310
35
35
55
Units
Units
mV
mV
mV
mA
ms
ps
ps
ns
ns
ps
ps
ps
ps
ps
ps
%
V