AD73411BB-80 AD [Analog Devices], AD73411BB-80 Datasheet - Page 14

• Manufacturer Part Number: AD73411BB-80
• Description: Low-Power Analog Front End with DSP Microcomputer
• Manufacturer: AD [Analog Devices]

AD73411
Sample Rate Divider
The AD73411 features a programmable sample rate divider that
allows users flexibility in matching the codec’s ADC and DAC
sample rates to the needs of the DSP software. The maximum
sample rate available is DMCLK/256, which offers the lowest
conversion group delay, while the other available rates are:
DMCLK/512, DMCLK/1024, and DMCLK/2048. The slowest
rate (DMCLK/2048) is the default sample rate. The sample
rate divider is programmable by setting bits CRB:0–1. Table V
shows the sample rate corresponding to the various bit settings.
DAC Advance Register
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(DMCLK/8); see Table VI. In certain
circumstances this can reduce the group delay when the ADC
and DAC are used to process data in series.
Note: The DAC advance register should be changed before the
DAC section is powered up.
DA4
0
0
0
—
1
1
DMCLK = 16.384 MHz.
DA3
0
0
0
—
1
1
DIR1
0
0
1
1
Table V. Sample Rate Divider Settings
Table VI. DAC Timing Control
DA2
0
0
0
—
1
1
DIR0
0
1
0
1
MCLK
(EXTERNAL)
SE
RESET
SDIFS
SDI
REGISTER A
CONTROL
DA1
0
0
1
—
1
1
8
SCLK Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
DA0
0
1
0
—
0
1
3
DIVIDER
REGISTER B
MCLK
CONTROL
Time Advance
0 ns
488.2 ns
976.5 ns
—
14.64 µs
15.13 µs
DMCLK
(INTERNAL)
8
REGISTER C
CONTROL
SERIAL REGISTER
8
SERIAL PORT
(SPORT)
OPERATION
Resetting the AFE Section of the AD73411
The RESET pin resets all the control registers. All registers are
reset to zero, indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As well
as resetting the control registers using the RESET pin, the device
can be reset using the RESET bit (CRA:7) in Control Register
A. Both hardware and software resets require four DMCLK cycles.
On reset, DATA/PGM (CRA:0) is set to 0 (default condition)
thus enabling Program Mode. The reset conditions ensure that
the device must be programmed to the correct settings after
power-up or reset. Following a reset, the SDOFS will be asserted
2048 DMCLK cycles after RESET going high. The data that
is output following RESET and during Program Mode is random
and contains no valid information until either Data or Mixed
Mode is set.
Power Management
The individual functional blocks of the AFE can be enabled
separately by programming the power control register CRC. It
allows certain sections to be powered down if not required,
which adds to the device’s flexibility in that the user need not
incur the penalty of having to provide power for a certain
section if it is not necessary to their design. The power control
register provides individual control settings for the major func-
tional blocks and also a global override that allows all sections to
be powered up by setting the bit. Using this method the user
could, for example, individually enable a certain section, such
as the reference (CRC:5), and disable all others. The global
power-up (CRC:0) can be used to enable all sections but if
power-down is required using the global control, the reference
will still be enabled, in this case, because its individual bit is set.
Refer to Table XI for details of the settings of CRC.
8
REGISTER D
CONTROL
8
REGISTER E
CONTROL
DIVIDER
SCLK
2
8
REGISTER F
CONTROL
SDOFS
SCLK
SDO