AD73411BB-80 AD [Analog Devices], AD73411BB-80 Datasheet - Page 7

• Manufacturer Part Number: AD73411BB-80
• Description: Low-Power Analog Front End with DSP Microcomputer
• Manufacturer: AD [Analog Devices]

Mnemonic
VINP
VINN
REFOUT
REFCAP
DGND
DVDD
ARESET
SCLK2
AMCLK
SDO
SDOFS
SDIFS
SDI
SE
AGND
AVDD
VOUTP
VOUTN
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL1/
PF6
BGA
Location
T1
T3
R7
R6
P4
P3
P5
P6
P7
R1
R2
R3
R4
R5
U1
U2
U5
U6
H3
N1
L1
F5
A2
B2
C2
D3
D2
C3
B3
D1
C1
Function
This pin allows direct access to the positive input of the sigma-delta modulator.
This pin allows direct access to the negative input of the sigma-delta modulator.
Buffered Reference Output, which has a nominal value of 1.2 V.
A Bypass Capacitor to AGND of 0.1 µF is required for the on-chip reference. The capacitor should be
fixed to this pin.
AFE Digital Ground/Substrate Connection.
AFE Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire analog front end, resetting the control registers and
clearing the digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data
or control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the
frequency of the master clock (AMCLK) divided by an integer number—this integer number being the product
of the external master clock rate divider and the serial clock rate divider.
AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP
and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the
DSP section.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK
period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and
is ignored when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked
on the negative edge of SCLK. SDI is ignored when SE is low.
SPORT2 Enable. Asynchronous input enable pin for SPORT2. When SE is set low by the DSP, the output
pins of SPORT2 are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order
to decrease power dissipation. When SE is brought high, the control and data registers of SPORT2 are at
their original values (before SE was brought low), however the timing counters and other internal regis-
ters are at their reset values.
AFE Analog Ground/Substrate Connection.
AFE Analog Power Supply Connection.
Analog Output from the Positive Terminal of the Output.
Analog Output from the Negative Terminal of the Output.
(Input) Processor Reset Input.
(Input) Bus Request Input.
(Output) Bus Grant Output.
(Output) Bus Grant Hung Output.
(Output) Data Memory Select Output.
(Output) Program Memory Select Output.
(Output) Memory Select Output.
(Output) Byte Memory Select Output.
(Output) Combined Memory Select Output.
(Output) Memory Read Enable Output.
(Output) Memory Write Enable Output.
(Input) Edge- or Level-Sensitive Interrupt Request
(Input/Output) Programmable I/O Pin.
(Input) Level-Sensitive Interrupt Requests
(Input/Output) Programmable I/O Pin.
PBGA BALL FUNCTION DESCRIPTIONS
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AD73411