AD7366_07 AD [Analog Devices], AD7366_07 Datasheet - Page 20

• Manufacturer Part Number: AD7366_07
• Description: True Bipolar Input, Dual 1 ?s, 12-/14-Bit, 2-Channel SAR ADCs
• Manufacturer: AD [Analog Devices]

AD7366/AD7367
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
the (logic) state of the
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366/AD7367
remaining fully powered at all times). Figure 22 shows the
general mode of operation of the AD7366 in normal mode,
while Figure 23 illustrates normal mode for the AD7367.
The conversion is initiated on the falling edge of
described in the Circuit Information section. To ensure that
the part remains fully powered up at all times,
at logic state high prior to the BUSY signal going low. If
is at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
The CS pin must be brought low to bring the data bus out of
CNVST
CNVST
BUSY
SCLK
BUSY
SCLK
CS
CS
CNVST
signal at the end of a conversion.
t
t
2
2
t
SERIAL READ OPERATION
t
SERIAL READ OPERATION
1
1
CNVST
t
t
Figure 22. Normal Mode Operation for the AD7366
CONVERT
Figure 23. Normal Mode Operation for the AD7367
CONVERT
CNVST
must be
CNVST
as
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1
1
t
t
3
3
three-state, subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366 while 14 SCLK cycles
are required to read from the AD7367. The D
to three-state when CS is brought high only. If CS is left low
for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles
for the AD7367, the result from the other on chip ADC is also
accessed on the same D
Figure 28 (see the Serial Interface section).
Once 24 SCLK cycles have elapsed for the AD7366 and 28
SCLK cycles for the AD7367, the D
state when CS is brought high and not on the 24
falling edge. If CS is brought high prior to this, the D
returns to three-state at that point. Thus, CS must be brought
high once the read is completed, as the bus does not auto-
matically return to three-state upon completion of the dual
result read.
Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
t
t
QUIET
QUIET
, has elapsed by bringing
14
12
OUT
line, as shown in Figure 27 and
OUT
line returns to three-
OUT
A and D
CNVST
OUT
th
lines return
or 28
OUT
low again.
OUT
B have
th
line
SCLK