AD7366_07 AD [Analog Devices], AD7366_07 Datasheet - Page 21

• Manufacturer Part Number: AD7366_07
• Description: True Bipolar Input, Dual 1 ?s, 12-/14-Bit, 2-Channel SAR ADCs
• Manufacturer: AD [Analog Devices]

SHUTDOWN MODE
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period
of inactivity and thus, shutdown. When the AD7366/AD7367
is in full power-down, all analog circuitry is powered down.
The falling edge of
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
returns low. If the
low then the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode the digital output
code from the last conversion on each ADC can still be read
from the D
low as described in the Serial Interface section. The D
return to three-state once
To exit full power-down and to power up the AD7366/AD7367,
a rising edge of
time has elapsed,
another conversion, as shown in Figure 24 (see the Power-Up
Times section for power-up times associated with the AD7366/
AD7367).
OUT
CNVST
BUSY
SCLK
pins. To read the D
CNVST
CS
CNVST
CNVST
CNVST
is required. After the required power-up
may be brought low again to initiate
signal is at logic low when BUSY goes
CS
initiates the conversion. The BUSY
is brought back to logic high.
t
OUT
2
data,
CS
must be brought
t
CONVERT
Figure 24. Autoshutdown Mode for AD7366
OUT
pins
ENTERS SHUTDOWN
Rev. 0 | Page 21 of 28
1
t
3
POWER-UP TIMES
The AD7366/AD7367 have one power down mode, which has
already been described in detail in the Shutdown Mode section.
This section deals with the power-up time required when coming
out of this mode. It should be noted that the power-up times (as
explained in this section) apply with the recommended capaci-
tors in place on the D
shutdown,
minimum of 70 μs, as shown in Figure 24.
When power supplies are first applied to the AD7366/AD7367,
the ADC can power up with
logic state. Before attempting a valid conversion,
be brought high and remain high for the recommended power-
up time of 70 μs. Then
conversion. With the AD7366/AD7367 no dummy conversion
is required before valid data can be read from the
If it is intended to place the part in shutdown mode when the
supplies are first applied, then the AD7366/AD7367 must be
powered up and a conversion initiated. However,
remain in the logic low state and when the BUSY signal goes
low, the part enters shutdown.
Once supplies are applied to the AD7366/AD7367, sufficient
time must be allowed for any external reference to power up and
to charge the various reference buffer decoupling capacitors to
their final values.
12
CNVST
SERIAL READ OPERATION
must be brought high and remain high for a
CAP
CNVST
A and D
CNVST
can be brought low to initiate a
t
POWER-UP
CAP
B pins. To power up from
in either the low or high
AD7366/AD7367
CNVST
CNVST
D
OUT
pins.
must
should