AD9231-20EBZ AD [Analog Devices], AD9231-20EBZ Datasheet
AD9231-20EBZ
Related parts for AD9231-20EBZ
AD9231-20EBZ Summary of contents
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... VIN–B VIN+B CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9231 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...
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... Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 AD9231-80 .................................................................................. 12 AD9231-65 .................................................................................. 14 AD9231-40 .................................................................................. 15 AD9231-20 .................................................................................. 16 Equivalent Circuits ......................................................................... 17 Theory of Operation ...................................................................... 19 ADC Architecture ...................................................................... 19 Analog Input Considerations .................................................... 19 REVISION HISTORY 10/09—Revision 0: Initial Version Voltage Reference ....................................................................... 22 Clock Input Considerations ...................................................... 23 Channel/Chip Synchronization ................................................ 25 Power Dissipation and Standby Mode ...
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... GENERAL DESCRIPTION The AD9231 is a monolithic, dual-channel, 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver- ter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...
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... Rev Page AD9231-65 AD9231-80 Typ Max Min Typ Max 12 Guaranteed Guaranteed 0.05 ±0.5 0.05 ±0.5 −1.5 −1.5 ±0.40 ±0.40 ±0.17 ±0.2 ±0.50 ±0.65 ±0.17 ±0.2 ±0.0 ±0.60 ±0.0 ±0.60 0.3 0.4 ±2 ±2 0.993 1.005 0.981 ...
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... Full 81 25°C 92/94 Full 25°C 83 25°C −98 25°C −97/−98 Full −90 25°C −97/−98 Full 25°C −92 25°C 90 Full −110 25°C 700 Rev Page AD9231 AD9231-65 AD9231-80 Min Typ Max Min Typ Max 71.4 71.3 71.3 71.2 70.5 71.0 70.9 70.1 69.0 69.0 71.3 71.2 71.2 71.1 70.0 70.9 70.8 70 11.6 11.5 11.5 11.5 11.5 11 ...
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... High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9231-20/AD9231-40/AD9231-65/AD9231-80 Temp Min Full Full 0.2 Full GND − 0.3 Full −10 Full −10 Full ...
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... – – – – – – – – 5 AD9231 Max Unit 625 MHz 80 MSPS rms Cycles μs ns Cycles ...
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... AD9231 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... ESD CAUTION Rev Page Airflow Velocity (m/sec) θ θ 2.0 1 specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9231 1, 4 θ Unit JB °C/W 12 °C/W °C/W ...
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... SDIO/DCS 45 SCLK/DFS 46 CSB 47 OEB 48 PDWN CLK+ 1 PIN 1 INDICATOR CLK– 2 SYNC AD9231 TOP VIEW D1B 9 (Not to Scale) DRVDD 10 D2B 11 D3B 12 D4B 13 D5B 14 D6B 15 D7B 16 Figure 5. Pin Configuration Description Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. ...
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... VIN−B, VIN+B Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev Page AD9231 ...
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... MHz 30.6 MHz MHz Figure 11. AD9231-80 Two-Tone FFT with f IN Rev Page 80MSPS –15 100.3MHz @ –1dBFS SNR = 69.5dB (70.5dBFS) –30 SFDR = 87.7dBc –45 –60 –75 3 – –105 –120 –135 0 4 ...
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... OUTPUT CODE Figure 14. AD9231-80 DNL Error with f 100 –20 –10 Figure 15. AD9231-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 100 150 200 –70 Figure 16. AD9231-80 SNR/SFDR vs. Input Amplitude (AIN) with f 0.4 ...
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... FREQUENCY (MHz) Figure 20. AD9231-65 Single-Tone FFT with 9.7 MHz Figure 21. AD9231-65 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz MHz IN Rev Page 120 SFDRFS ...
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... FREQUENCY (MHz) Figure 24. AD9231-40 Single-Tone FFT with f 120 100 9.7 MHz Figure 25. AD9231-40 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz IN Rev Page SFDRFS SNRFS SFDR SNR 0 –70 –60 –50 –40 –30 – ...
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... FREQUENCY (MHz) Figure 27. AD9231-20 Single-Tone FFT with f 120 100 –70 = 9.7 MHz Figure 28. AD9231-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz IN Rev Page SFDRFS SNRFS SFDR SNR –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBc) ...
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... Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Rev Page DRVDD Figure 32. Equivalent Digital Output Circuit DRVDD 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ AVDD 375Ω RBIAS AND VCM Figure 34. Equivalent RBIAS and VCM Circuit AD9231 ...
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... AD9231 DRVDD AVDD 30kΩ 350Ω CSB Figure 35. Equivalent CSB Input Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit VREF Figure 37. Equivalent VREF Circuit Rev Page AVDD 375Ω 7.5kΩ ...
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... THEORY OF OPERATION The AD9231 dual ADC design can be used for diversity recep- tion of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f ...
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... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9231 (see Figure 41), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... Figure 45. Differential Input Configuration Using the AD8352 Rev Page 10µF AVDD 1kΩ R VIN+x 0.1µF 49.9Ω 1kΩ AVDD C 1kΩ R VIN–x 10µF 0.1µF 1kΩ Figure 43. Single-Ended Input Configuration R VIN+x ADC C R VCM VIN–x R VIN+x C ADC R VCM VIN–x 0.1µF AD9231 ADC ...
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... SENSE Voltage (V) Fixed Internal Reference AGND to 0.2 Fixed External Reference AVDD If the internal reference of the AD9231 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 47 shows how the internal reference voltage is affected by loading. ADC CORE 0 ...
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... Jitter Considerations section. Figure 50 and Figure 51 show two preferred methods for clock- ing the AD9231 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ...
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... CLK+ performance characteristics. ADC 100Ω The AD9231 contains a duty cycle stabilizer (DCS) that retimes 0.1µF the nonsampling (falling) edge, providing an internal clock CLK– signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9231 ...
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... For more information, see the AN-501 Application Note and the AN-756 Application Note available on www.analog.com. CHANNEL/CHIP SYNCHRONIZATION The AD9231 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence ...
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... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9231. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9231 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9231 provides two data clock output (DCO) signals intended for capturing the data in an external register ...
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... AD9231. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9231 signal path. Perform the BIST test after a reset to ensure the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... AD9231 SERIAL PORT INTERFACE (SPI) The AD9231 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9231. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9231 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). ...
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... Bit 6 Chip Configuration Registers 0x00 SPI port 0 LSB configuration first (global) 0x01 Chip ID (global) 8-bit chip ID bits [7:0] AD9231 = 0x24 0x02 Chip grade Open Speed grade ID [6:4] (global) 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Device Index and Transfer Registers 0x05 Channel index ...
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... AD9231 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x0E BIST enable Open Open 0x10 Offset adjust 8-bit device offset adjustment [7:0] (local) (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS 0x15 OUTPUT_ADJUST 3.3 V DCO ...
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... Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Rev Page AD9231 Default Bit 0 Value Bit 1 (LSB) ...
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... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 42. RBIAS The AD9231 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... AD9231BCPZ-20 –40°C to +85° AD9231BCPZRL7-20 –40°C to +85°C 1 AD9231-80EBZ 1 AD9231-65EBZ 1 AD9231-40EBZ 1 AD9231-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW ...
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... AD9231 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08121-0-10/09(0) Rev Page ...