AD9231-20EBZ AD [Analog Devices], AD9231-20EBZ Datasheet - Page 8
AD9231-20EBZ
Manufacturer Part Number
AD9231-20EBZ
Description
12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
AD [Analog Devices]
Datasheet
1.AD9231-20EBZ.pdf
(36 pages)
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AD9231
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
SYNC
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
CLK+
t
Figure 4. SYNC Input Timing Requirements
SSYNC
Rev. 0 | Page 8 of 36
t
HSYNC
Min
2
2
40
2
2
10
10
10
10
Typ
0.24
0.40
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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