AD5760ACPZ AD [Analog Devices], AD5760ACPZ Datasheet - Page 22

• Manufacturer Part Number: AD5760ACPZ
• Manufacturer: AD [Analog Devices]

AD5760
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Reset Function ( RESET )
The
either by asserting the RESET pin or by using the reset function
in the software control register (see
is not used, hardwire it to IOV
Asynchronous Clear Function ( CLR )
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 16-bit clearcode value is
programmed to the clearcode register (see
necessary to maintain
to complete the operation (see
is returned high, the output remains at the clear value (if LDAC
Table 8. Hardware Control Pins Truth Table
LDAC
X
X
0
0
1
1
0
1
0
1
Table 9. DAC Register
MSB
DB23
R/W
R/W
1
X is don’t care.
X is don’t care.
1
1
AD5760
CLR
X
X
0
1
0
1
0
1
0
1
X
1
X
can be reset to its power-on state by two means:
DB22
0
1
1
RESET
0
1
1
1
1
1
1
1
1
1
CLR low for a minimum amount of time
Register address
DB21
0
CC
Figure 2
Function
The
The
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clearcode register value.
The output remains set according to the DAC register value.
The output remains at the clearcode register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clearcode register value.
The output is set according to the DAC register value.
.
AD5760
AD5760
Table 13
). When the
Table 12
DB20
1
). If the
is in reset mode. The device cannot be programmed.
is returned to its power-on state. All registers are set to their default values.
). It is
CLR signal
RESET pin
DB19 to DB4
DAC register data
16 bits of data
Rev. B | Page 22 of 32
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
The following equation describes the ideal transfer function of
the DAC:
where:
V
V
D is the 16-bit code programmed to the DAC.
REFN
REFP
is the positive voltage applied at the V
is the negative voltage applied at the V
V
OUT
DB3
X
=
1
(
V
REFP
−
2
DB2
X
V
16
1
REFN
)
×
Table 13
D
DB1
X
+
REFP
REFN
1
V
REFN
Data Sheet
input pin.
).
input pin.
DB0
X
1
LSB