AD5760ACPZ AD [Analog Devices], AD5760ACPZ Datasheet - Page 23

• Manufacturer Part Number: AD5760ACPZ
• Manufacturer: AD [Analog Devices]

Data Sheet
Control Register
The control register controls the mode of operation of the
AD5760.
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the CLR pin or CLR bit in the software control register
Table 10. Control Register
MSB
DB23
R/
R/
Table 11. Control Register Functions
Bit Name
Reserved
RBUF
OPGND
DACTRI
BIN/2sC
SDODIS
R/
Table 12. Clearcode Register
MSB
DB23
R/W
R/W
1
X is don’t care.
W
W
W
DB22
0
Register address
DB22
0
Description
These bits are reserved and should be programmed to zero.
Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors R
an external amplifier to be connected in a gain of two configuration. See the
1: (default) the internal amplifier, A1, is powered down and Resistors R
Figure 53, so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the R
and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the
section for further details.
Output ground clamp control.
0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) the DAC is in tristate mode.
DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
Read/write select bit.
0:
1:
DB21
1
AD5760
AD5760
Register address
DB20
0
is addressed for a write operation.
is addressed for a read operation.
DB21
1
DB19 to DB11
Reserved
DB20
1
DB10
Reserved
DB19 to DB4
Clearcode register data
16 bits of data
DB9
Rev. B | Page 23 of 32
DB8
0000
DB7
FB
and R1 are connected in series, as shown in Figure 54. This allows
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
Control register data
DB6
FB
DB5
SDODIS
and R1 are connected in parallel, as shown in
AD5760
BIN/2sC
DB4
DB3
X
1
Features section for further details.
DB3
DACTRI
DB2
X
1
X
DB2
OPGND
AD5760
DB1
X
1
X
DB1
RBUF
AD5760
Features
DB0
X
DB0
Reserved
1
X
LSB
LSB
FB