HI5766_05 INTERSIL [Intersil Corporation], HI5766_05 Datasheet
HI5766_05
Related parts for HI5766_05
HI5766_05 Summary of contents
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TM Data Sheet 10-Bit, 60MSPS A/D Converter The HI5766 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process designed for high speed applications where wide bandwidth and low power consumption are essential. Its 60MSPS speed is ...
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Functional Block Diagram S/H + ∑ ∑ AGND CC 2 HI5766 BIAS STAGE 1 2-BIT 2-BIT FLASH DAC STAGE 8 2-BIT 2-BIT FLASH DAC STAGE 9 ...
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Typical Application Schematic 2.5V 2.0V (OPTIONAL CLOCK Pin Description PIN NO. NAME DESCRIPTION 1 DV Digital Supply (+5.0V). CC1 2 DGND1 Digital Ground Digital Supply (+5.0V). CC1 4 DGND1 Digital Ground. 5 ...
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Absolute Maximum Ratings T A Supply Voltage AGND or DGND . . . . . . . . . . DGND to AGND . . . . . . . . . . ...
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Electrical Specifications 10pF Unless Otherwise Specified (Continued) PARAMETER ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range ( Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance ...
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Electrical Specifications 10pF Unless Otherwise Specified (Continued) PARAMETER TIMING CHARACTERISTICS Aperture Delay Aperture Jitter Data Output Hold Data Output Delay Data Output Enable Time ...
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Timing Waveforms ANALOG INPUT CLOCK INPUT INPUT S/H 1ST STAGE 2ND ...
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Typical Performance Curves INPUT FREQUENCY (MHz) FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY 85 -2HD 75 SFDR 65 -3HD INPUT FREQUENCY (MHz) NOTE: SFDR depicted here does ...
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Typical Performance Curves SND MSPS 10MHz 0.5V REF REF 47 2.25 2.30 2.35 2.40 2.45 ...
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Typical Performance Curves 8.9 8.7 60 MSPS/1MHz 8.5 8.3 60 MSPS/10MHz 8.1 7.9 7.7 7.5 -40 - TEMPERATURE ( FIGURE 15. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE 1200 1000 800 600 400 200 0 -40 -20 0 ...
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Typical Performance Curves 3.30 3.20 3.10 3.00 -40 - TEMPERATURE ( FIGURE 21. DC BIAS VOLTAGE (V DC -100 Detailed Description Theory of Operation The HI5766 is a 10-bit fully differential sampling pipeline A/D converter with digital error ...
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S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter ...
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The resistors Figure 26 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from will help filter any high IN IN frequency noise on the inputs, ...
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DIFFERENTIAL INPUT CODE CENTER VOLTAGE DESCRIPTION ( +Full Scale (+FS LSB 0.499756V + LSB 0.498779V LSB 732.422µ LSB -244.141µV ...
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V = 0.5 dB. CORR V adjusts the SINAD, and hence the ENOB, for the CORR amount the analog input signal is below full scale. Signal To Noise and Distortion Ratio (SINAD) SINAD is the ratio of the measured ...
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Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Aperture Delay ( Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the ...